RE: 64b/66b Synchronization / state machines
Removing the effect of hi_ber = true on the receive state machine was
my error in redrawing the state machines. That will be fixed by ORing
hi_ber = true with the other conditions that cause transition to the
RX_INIT state of the receive state machine.
On why the TX state machine is checking the type of the next code block
when receiving a T (which is I assume the three bit error checking to
which you refer), there were a number of changes to both state machines
to implement changes in error handling and to make the machines a bit
more rigorously defined. In doing that, I made them a bit too parallel.
Errors can certainly happen across a XAUI and the signal may have gone
through two XGXS sublayers and a XAUI before reaching the transmit
state machine so we need to deal with errors into the transmit machine.
However, checking that a T is followed by an S or C frame in the
receive state machine is enough protection. Therefore, the checks for
T_TYPE_NEXT in the transmit state machine will be removed.
From: David Gross [mailto:firstname.lastname@example.org]
Sent: Tuesday, November 14, 2000 11:31 AM
Cc: email@example.com; firstname.lastname@example.org;
Subject: 64b/66b Synchronization / state machines
I was hoping you could shed some light on some questions I've been
In reading clause 49 of D1.1 and comparing it to D1.0 I have noticed
that there is no longer a variable called sync_done. My main question
deals with D1.0 Fig 49-11 and D1.1 Fig 49-12 (i.e: The Receive state
machine). In D1.0, the criteria for going through the machine was that
sync_done = true. In the newer version, this has been reduced to
frame_lock = true. sync_done was defined as being = frame_lock *
!hi_ber. So, my question is why has the BER monitoring been removed as a
condition for the receive state machine? Is it that if there is a high
BER (>16 in ~125us) but we can still maintain frame_lock we don't care
about the BER and just continue doing our sequence monitoring? (Then why
monitor the BER at all?)
Another question I have is why the Transmit state machine was given the
3-bit error protection similar to the RX side (dealing with the D -> T).
I'm just curious why this was only put in now. Is it that we can't rely
on the XGMII being virtually fault free? (I think this was the original
reason why it wasn't in the first TX state machine)