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Re: Clause 48: Data Delay Estimation


The Clause 48 maximum allowable lane-to-lane skew is <41 bits per table
48-4. 85 bits is the maximum skew that the ||A|| spacing protocol can
handle. I roughly calculated the delay estimates based on the maximum
allowable skew, not the protocol deskew capability. Please consider this
information and tell me if you still believe that the delay estimate is
too low.

Best Regards,

Boaz Shahar wrote:
> Hi Rich,
> I think that the the data delay estimation in section is slightly
> optimistic:
> The maximal skew between lanes is said to be 85 bits (page 148 in D1.1). The
> maximum delay estimation is 33.6n which is 105 UI. This leaves about 20 bit
> delay for internal logic. If the architecture is based on 156.25Mhz clock,
> any clock cycle is 20 bits. So you are left with only one extra sample!
> Even for lower skew estimation, I think that a delay estimation should leave
> a gauardband for couple of samples, typically about 4 samples due to logic
> and circuit issues. 4 samples with 156.25 clock is additional 80 bits only
> for implementation  delay within the PCS.
> So, I propose to increase the number by about 80 bits to something around
> 180 bits (about 60ns)
> Best Regards,
> Boaz
Richard Taborek Sr.                 Phone: 408-845-6102       
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