Re: Comment on D2.0 Clause 51, Table 51-6 - magnitude of TD
In a message dated 12/8/00 3:46:40 AM Pacific Standard Time,
> This message for Justin Chang.
> I see you have added a note in draft 2.0 pointing out that the value of TD
> the variation of PMA_TXCLK_SRC to PMA_TXCLK delay - is possibly too large
> 30ns. As we discussed at the Tampa meeting, I would still like to
> reason why TD was originally proposed to be as large as 30ns. TXCLK_SRC is
> used to clock the 16 bit parallel data out of the PCS, together with the
> TXCLK. It should be possible for this delay variation to be very small - a
> few ns at the most. I still believe that most Serdes vendors will have
> trouble meeting a value as large as 30ns. I am intending to propose a much
> smaller value in my ballot comment, but would appreciate some initial
> discussion too confirm the rationale. Would a conference call be valuable?
I am quite in agreement that we can reduce this number. The question is what
to reduce it to. I have inputs from our engr team on this ... see my earlier
msg onto the reflector but I am open for more specifics. I will set up a
call to those interested.
For any and all interested in having a conference call
on this. Let me know your availability. I would like to set this call to be
Tuesday, Dec 12 sometime ... tentatively 11AM PST time, 2PM EST for one
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