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Clause 45 (D2.0) Questions


Hello There,

1)The status bit "XAUI Transmit link status" in the PHY-XGXS status register
(table 45-29) seems to be duplicated in the "Lane Status Register". The same
duplication occurs in the DTE-XGXS register description as well.  Why this
is needed?

2)The term "Transmit signal clock to output delay" (Section 45.4.5.8) refers
to the delay between the MDC edge to the MDIO data? If so, what is reffered
by the term "MDIO clock to output delay"?

Thanks,
Boaz