Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

RE: PCS FIFO Empty condition

Title: RE: PCS FIFO Empty condition

Hi Ben,

Thanks a lot for ur reply.

I was talking about the FIFO used for clk tolerances.
I just repeat the conclusion, PHY should not let fifo go empty in between the packet data, maintaining pkt-integrity (by adjusting the IPG). My quenstion was design specfic. If due to some mechanism problems, suppose, the fifo goes empty, then the idle data should be sent on the line. No error coulmn should be inserted.


-----Original Message-----
From: Ben Brown []
Sent: Friday, January 05, 2001 9:17 PM
To: 802.3ae
Subject: Re: PCS FIFO Empty condition


I'm going to suggest that your FIFO is an implementation
specific entity. There is nothing in the standard that
requires the use of a FIFO in the PCS.

If there is no incoming data stream, it is expected that
local fault will be generated towards the RS.

If you are referring to clock tolerance adjustments, an
extra column of IDLEs are inserted during the IPG.


> Anupama Agashe wrote:
> Hi,
> What action should be taken by the transmit PCS FIFO, when it goes
> EMPTY (may be in between a packet-data, or IPG) due to some
> conditions?
> My understanding is that it should continuously insert idles till
> normal condition is restored. But is it also necessary to specifically
> insert atleast one ERROR column under this condition? The receive MAC
> on the other side is going to discard the respective packet under both
> the conditions (since packet gets broken). So, does the PHY need to
> indicate empty through the error indication?
> regards,
> Anupama

Benjamin Brown
2 Commerce Park West
Suite 104
Bedford NH 03110
603-641-9837 - Work
603-491-0296 - Cell
603-626-7455 - Fax
603-798-4115 - Home Office