Re: Clock Tolerance and WAN PHY
I'm sorry to have confused you with my comments. Please allow me to try
and clear up any confusion I may have caused.
The primary purpose of the 10 Gigabit Ethernet project is to provide the
customer with the next logical speed upgrade to 1 Gigabit Ethernet,
which provide the same for 100 Megabit Ethernet, which in turn...
Supporting Ethernet over SONET or SDH or OTN or Digital Wrapper, etc. is
NOT a purpose. This effort is merely a goal or objective which will be
met, one way or another, while addressing the primary purpose. The
P802.3ae Task Force has seen fit to set an objective to develop a WAN
PHY to support Ethernet over SONET. I merely pointed out in my previous
note on this thread that the WAN PHY is only one of at least seven
current industry and standards activities to map Ethernet to the
existing WAN infrastructure. I believe that at least five of the seven
methods have been mentioned in this thread alone.
It should be clear that without an optional objective to support the WAN
PHY, that the 10 Gigabit Ethernet PHY would be developed to support LAN
and MAN applications anyway. This is because:
a) IEEE 802 is the LAN/MAN Standards Committee (LMSC);
b) IEEE 802.3z (Gigabit Ethernet) has already opened up the barn door
with its Fiber Optic technology, significantly increasing the link
distance supported by prior Ethernet physical layers and capable of
addressing MAN and WAN applications in addition to LAN;
c) There are a plethora of startups and large corporations already using
or eying Gigabit Ethernet and 10 Gigabit Ethernet LAN PHY equipment for
MAN and WAN application without requiring ATM or SONET at all.
Now back to the subject of this thread...
Clock Tolerance: +/-100 PPM is more than adequate for the 10 Gigabit
Ethernet LAN PHY. In fact, this tolerance is fairly difficult to achieve
as it corresponds to the 10.3125/3.125 Gbps line rate for the
Serial/WWDM, respectively, rather than the clock oscillator. The clock
oscillator frequency may actually be ~1/100 the line rate and is likely
multiplied up to the line rate.
In the interest of standing a chance of meeting the IEEE P802.3ae
economic feasibility criteria, I strongly suggest keeping the clock
tolerance of the Ethernet PHY at +/- 100 PPM. This goes for both the LAN
and WAN PHYs since the WAN PHY would benefit greatly from the sharing
common components with the LAN PHY.
Roy Bynum wrote:
> You have a very good a presenting that would seem reasonable to those who
> don't have any experience in attempting to implement what you are
> proposing. The objectives of P802ae include a WAN PHY. What constitutes a
> WAN PHY has been explained to the group by those of us that have worked in
> a WAN optical environment. You keep miss representing the requirements of
> a WAN PHY by presenting a LAN implementation as a WAN. It works very well
> at confusing those that are attempting to gain an understanding of what the
> issues are.
> Those of us that have worked in the WAN optical environment are not
> confused by your comments. Those of us that have worked in the WAN optical
> environment would like to have the opportunity to educate those that would
> actually like to gain a understanding of what the real world requirements are.
> Thank you,
> Roy Bynum
> At 06:39 PM 1/24/01 -0800, Rich Taborek wrote:
> >I strongly agree with your suggestion below, and Brad Booth's note along
> >the same vein, to leave any conversion between Ethernet and SONET at the
> >ELTE level. This would allow the LAN PHY, Serial or WWDM, it doesn't
> >really matter since the ELTE does the required conversion, to natively
> >serve LAN, MAN and WAN applications at the lowest possible cost. At the
> >same time, the same LAN PHY can attach to an ELTE and operate in "WAN
> >PHY mode" to support SONET/SDH. The latter would be applicable to those
> >legacy SONET/SDH core applications, again, AT THE LOWEST POSSIBLE COST.
> >Of paramount importance to the customer is our ability to meet the
> >Economic Feasibility PAR criteria. In a nutshell this criteria states
> >that the cost of 10GE shall be ~3.5X the cost of Gigabit Ethernet at
> >product maturity. I don't visualize copying SONET/SDH, requiring +/-20
> >PPM clock tolerance, supporting overhead bytes, etc. as helping us meet
> >our economic feasibility objectives. However, I do see straightforward
> >mappings, the same clock tolerances as Gigabit Ethernet (+/-100 PPM),
> >protocol simplicity, relaxed jitter specifications, etc. as meeting the
> >objectives. The latter are characteristics of the LAN PHY, the former
> >are characteristics of the WAN PHY.
> >Ethernet has met its economic feasibility objectives for three
> >generations through selection and leverage of low cost physical layers.
> >This will happen again through simple extension of Gigabit Ethernet
> >physical layer technology as is the case for the LAN PHY. It should be
> >obvious to the most casual observer that the more that SONET/SDH is
> >leveraged for 10GE, the higher the total 10GE solution cost will be.
> >Just reading though the notes of this thread, it looks like there's
> >about as many ways to map Ethernet to SONET as there are to skin a cat.
> >Here are some of the ones from this thread:
> >1) Ethernet over LAPS, ITU-T SG7
> >2) Packet over SONET, ???
> >3) Ethernet over SONET/SDH, ITU-T SG7 X.86
> >4) Ethernet over SONET/SDH, T1X1
> >5) Digital Wrapper, ITU-T ???
> >6) G.709, ITU-T (Same as Digital Wrapper???)
> >7) IEEE P802.3ae WAN PHY
> >I'm kind of partial to Ethernet over Ethernet.
> >Best Regards,
> >Boaz Shahar wrote:
> > >
> > > MAC - (Serial lan phy) - ELTE - (sonet ring) - ELTE - (serial lan phy)
> > - MAC
> > >
> > > Anyway, the WIS takes 64/66 frames and encapsulates them into the SONET
> > > frame. So just take the 66/64 bit stream that comes to the ELTE through the
> > > serial LAN and do the same there with a full SONET compliancy. Is that
> > > correct? What is the advantage comes from doing the WIS in the PHY? (The
> > > rate is not a problem Just operate the MAC in SONET rate as you do anyway
> > > and put the FIFO in the ELETE as you anyway have in the WIS)
> > >
> > > Thanks (Sorry for the long mail)
> > > Boaz
Richard Taborek Sr. Phone: 408-845-6102
Chief Technology Officer Cell: 408-832-3957
nSerial Corporation Fax: 408-845-6114
2500-5 Augustine Dr. mailto:rtaborek@nSerial.com
Santa Clara, CA 95054 http://www.nSerial.com