XAUI jitter test pattern proposal

["Tom Lindsay" <Tom.Lindsay@vixel.com>]

I accepted an action to create a (jitter) test pattern for XAUI. My proposal
is below. If I have posted to a wrong reflector, I apologize, and let me
know.

This is the payload portion only, given for each of the 4 lanes. That is, this pattern still must be built into an aggregate payload, where the contents of the 4 lanes are combined. I have not done that. The length of this pattern is a total of 376 bytes, such that for 4 lanes combined, the total payload is 1504 bytes (I was told that 1518 was a maximum, but for other reasons, the pattern length should be divisible by 16).

The pattern interposes the 2 character sequence Mysticom used in their "killer" jitter pattern between the two sequence components that form the core of CJTPAT from Fibre Channel. The durations of the CJTPAT components are reduced to fit into the payload. PLL settling may be somewhat sacrificed, but I believe the durations are still sufficient to stress typical parts. The relative durations still assume that PLL response time is inversely proportional to input pattern transition density. This may want to be challenged. (Approximately) 8 bytes of the killer pattern appear in each instance.

Each 376 byte sequence actually is 2 times through a 188 byte sequence, such that both disparities are tested.

Here is the 188 byte sequence:
D30.3              132 times
D20.7/D11.7 pair   3 times
D20.7/D11.5        1 time
D21.5              40 times
D20.7/D11.7 pair   4 times
Repeat above, but now with alternate disparity

Here is the 376 byte sequence showing the D character, hex code, starting running disparity, serial sequence, and ending running disparity. Note that if the initial running disparity is + (- is shown), then the 2 188 byte sections of the pattern will be effectively swapped. As shown below, with + starting disaprity, the first half of the pattern provides the more stressful serial sequences of the "killer" pattern.
Start
D30.3 7E - 0111100011 +
... (cont'd) ...
D30.3 7E + 1000011100 -
D20.7 F4 - 0010110111 +
D11.7 EB + 1101001000 -
D20.7 EB - 0010110111 +
D11.7 EB + 1101001000 -
D20.7 F4 - 0010110111 +
D11.7 EB + 1101001000 -
D20.7 F4 - 0010110111 +
D11.5 AB + 1101001010 +
D21.5 B5 + 1010101010 +
... (cont'd) ...
D21.5 B5 + 1010101010 +
D11.7 EB + 1101001000 -
D20.7 F4 - 0010110111 +
D11.7 EB + 1101001000 -
D20.7 F4 - 0010110111 +
D11.7 EB + 1101001000 -
D20.7 F4 - 0010110111 +
D11.7 EB + 1101001000 -
D20.7 F4 - 0010110111 +
Repeat above, but now with alternate disparity
D30.3 7E + 1000011100 -
... (cont'd) ...
D30.3 7E - 0111100011 +
D20.7 F4 + 0010110001 -
D11.7 EB - 1101001110 +
D20.7 EB + 0010110001 -
D11.7 EB - 1101001110 +
D20.7 F4 + 0010110001 -
D11.7 EB - 1101001110 +
D20.7 F4 + 0010110001 -
D11.5 AB - 1101001010 -
D21.5 B5 - 1010101010 -
... (cont'd) ...
D21.5 B5 - 1010101010 -
D11.7 EB - 1101001110 +
D20.7 F4 + 0010110001 -
D11.7 EB - 1101001110 +
D20.7 F4 + 0010110001 -
D11.7 EB - 1101001110 +
D20.7 F4 + 0010110001 -
D11.7 EB - 1101001110 +
D20.7 F4 + 0010110001 -
End

Comments?

Thanks,
Tom Lindsay
Vixel
425/806-4074
 

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