RE: 49.2.14.3 Jitter test mode control
Hi Alex,
1. You have found an inconsistency. The jitter test was voted in at the
January meeting, but with details left up to the editors. At the editor's
meeting, we agreed that the transmit and receive should be controlled
separately. The intent was to have separate bits to control them in the PCS
registers. Ed wasn't there and apparently didn't get the word. I suggest you
submit a comment.
2. I thought about putting a delay in to start the counter in the jitter
receiver, but the receiver never knows when the transmitter was put into
jitter test mode, how long the link is (and thus how much delay there might
be before the jitter test pattern starts to reach it), etc. Therefore, it
should be up to the manager that is controlling the operation (and which
should have more smarts than a PCS chip anyway) to get both ends into test
mode, wait a bit, and then read the counter to clear it before starting to
read the counter to accumulate bit error statistics. The PCS just starts the
counter as soon as it is put into jitter receive test.
Regards,
Pat
-----Original Message-----
From: Alex Deng [mailto:adeng@cisco.com]
Sent: Friday, February 16, 2001 11:02 AM
To: Pat Thaler; stds-802-3-hssg@ieee.org
Cc: Alex Deng
Subject: 49.2.14.3 Jitter test mode control
Hi Pat,
In 49.2.14.3, there are two variables: tx_jitter_test and
rx_jitter_test.
But I can only find 1 bit in PCS control 2 register(Page 206) which
called " jitter test mode".
My questions are:
1. Where are these two variables tx_jitter_test and rx_jitter_test come
from?
2. Before the jitter pattern data reach jitter pattern checker, the
checker
will always generate error, when should I start the counter for
jitter error?
Thanks,
--Alex