Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

MDIO Electricals


As one of the suppliers of PMDs we have been in a position to look at the
specs of a number of XGMII to XAUI, XAUI to 10 Serial, and XSBI to 10G
serial VLSI for incorporation into optical transceivers we are
considering/developing such as XGP and XSBI VSR. We have noted that most
XAUI VLSI refer CMOS I/O to 1.8V or 3.3V, often with 3.3V tolerance. Adding
circuitry in the PMD to down-regulate and translate from 3.3V or 1.8V to
lower I/O voltages will impose negative space, power and cost impacts that
will be passed to the end user (who expect ever cheaper PMDs). 

General observations/comment/proposal:

-There are a number of parameters listed in the Clause 45 Proforma
( which are not in the 45.4.1 table that should be picked up in the
next rev?

-The Clause 45 Annex voltage translator circuit suggested for Clause 45 to
Clause 22 MDIO compatibility is likely to carry royalty issues with Philips
Patent # 5,689,196, and again, would impose an undesirable circuit expense
to the VLSI and/or PMD.

-The D2.1 timing does not appear to recognize the drive current and
capacitive load issues with 32 devices on the bus, i.e. is a 10ns setup and
hold achievable with a fully loaded bus at full speed operation? If the VLSI
or PMD provide an internal weak pull-up, will 32 of these in parallel allow
proper bus pull down?

-There is an implication that MDIO is a CMOS point to point interface, or an
open drain bus, and an Iol/Ioh of 100uA is inadequate for the latter. What
are the OEM MAC designers planning to drive? We have already discussed
system cards with OEMs planning four to eight XGPs per card.

-The ideal PMD (XGP for example) would have one pair of MDIO pins, with
internal connections to the VLSI and to the microcontroller providing PMD
management(temperature ,etc.).  How would the bus timing accommodate 16 PMDs
with two internal devices/stubs each?

-It is unlikely that commodity suppliers of microcontrollers and EEPROMs
will flock to a sub 1.8V bus, making the current spec an exclusively VLSI
play, and forcing the PMD management to another set of precious PMD conector
pins. (we are pushing to avoid this in the XGP MSA)

A possible path to harmony on all points would be to morph the MDIO
electrical/timing definition a "near" clone of the I2C bus with the
following benefits:

 -the I2C electrical/timing definition does not appear to be covered by
Philips patents (SMBus cloned it)
 -the I2C switching levels scale with VDD over the Clause 22 and 45 VDD
ranges(Maintaining Clause 22 compatibility)
 -I2C now has a 3.4MHz mode (How does MDIO get to 25MHz with 32 devices
attached anyway?)
 -I2C preserves the legacy PMD management interface and OEM ASIC investments

   -(GBIC is I2C, and a 1Gb 802.3 PMD after all...)
 -The I2C bus performance is well known and defined
 -The PMD can adapt to the differing signaling protocols between I2C and

References to GBIC 5.5, PHY Management a.k.a Transceiver Management Services
(TMS)in the SFF group,Current I2C and SMBus specs, etc. are available at:

We hope this will spark a healthy discussion to the benefit of all.


Bryan Yunker
VP Engineering
Picolight, Inc.
303-530-3189 x299