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Clause 48 Questions

Couple of  questions occurred to me while reading D2.3:

1) In previous drafts (I think it was D2.1), the specified delay from Start
sampling to MDI output is 1024BT, and the delay from MDI input to XGMII
Start is 1024BT as well (Table 48-6, D2.1). 

In D2.3 the table is missing, and the text says that the sum of the above
delays is 1024BT. This means about half the delay for the receive and the
transmit. Is that the intention? And if so: What is the reason for the big

2) Referring the recent discussion about propagating the error after the
packet to within packet boundary: This requires two additional samples of
the data, because sometimes you have to generate error in a column that was
there two clocks before. This increases the delay at least in two samples in
each lane, or 8 data bytes, or 80 BT?

3)What is the delay constraint for the PMA of 10GBASE-X?