[802.3ae] M0 Line remote error indiation support for WIS
Hello all,
WAN interface sub-layer support only M1 byte for STS-N line remote error
indication as described in the structure of section and line overhead
generated by WIS in figure 50-8 of P802.3ae_D3_2.cb
ITU-T G.707 Revision 2000 has added M0 Line-REI byte in addition to M1 for
STM-64 (10G) frames and above ( 40G) . The M0 byte will be located right
before the M1 byte. The M0 and M1 bytes convey the count of interleaved bit
blocks that has been detected in the error by the BIP-1536 (in the range of
[0, 1536]). M0 bit 1 is most significant bit and M1 bit 8 is least
significant bit. If interworking with old equipment supporting the single
byte REI in M1, the value conveyed is truncated at 255 and inserted in M1.
For backward compatibility, ITU-T specifies that for 10G frames, new
equipment (10/2000 onward) should be able to support both modes : one-byte
L-REI (M1) with a truncated value, as well as 2-byte L-REI (M0M1) with
non-truncated REI.
Since 10 Gbit/s WIS is defined after October 2000 and WAN-PHY would
interface to SONET/SDH infrastructure. So WIS should also support the M0
with backward compatibility. The interworking should be configured by the
management system.
What you all think about the M0 support in WIS .
Pankaj Kumar
Optical Products Group
Intel corporation
201 Mission St. 5th Floor
San Francisco, Ca, 94105
(415) 536-2166
pankaj.kumar@intel.com <mailto:pankaj.kumar@intel.com>