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Hi Bob:
How are you.
I have a question about the 10G DTE(PHY) XGXS Lane
status register in Draft 5.0
bit 12 (5.24.12 or 4.24.12), lane alignment status
which indicates
all four lanes are in sync (generated by sync state machines. as shown in Table 48-8 on page 323 and 48.2.6.1.3 on page
327).
In previous Draft3.4, this bit indicated
all four lanes are in Sync and Deskewed.
In other word, should this bit be Align_status? or
should it be logic 'AND' of the Sync_status bits from all 4 lanes ?
Please advise me which one is correct.
Best Regards
Steven Shen
Siliconbridge Inc.
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