Serial PMD clock scheme options
An important part of a Serial PMD design is a decision on internal
clocking architecture. Using 64B66B code as an example, I have
summarized two possible clocking scheme options in a document. With
David Law's help, I have placed it at the following URLs:
Perhaps there are other clocking schemes you can suggest. The next
step depends on our implementation preference.
Proponents of convergence may suggest that it's best to consolidate
all possible clocking schemes into a single design. Proponents of
the opposite approach may suggest that it is best to allow a couple
of different implementations, each one optimum in its own framework.
I invite your comments.