Re: short haul copper
I agree with Kameran's two other reasons. To add to the second one, the
proposal Ed Cady and I aired in Montreal was the simplest 10 Gbps scheme we
could come up with. It suggested neither any equalization in the cable nor
compensation in the logic. A slightly more complex design could potentially
attain distances in the range of existing GbE short-haul copper distances:
those being in the range of 25 m on Twin-Ax.
> I think 2 other reasons why the short haul was not approved
> in HSSG:
> 1) the group consists mostly of fiber people (copper people are not
> heavily attending the HSSG meetings...)
> 2) I wasn't there, but I heard the motion proposed 10Gb/s over 10m
> distance, and that was a concern to many people I talked to. It
> seems that 30m is a more convincing number.
> In response to your proposal of using quad twinax, 2up-2down, or
> Rich's 1up-1down, I would like to propose a way to choose which
> approach is the most suitable for the given channel (twinax).
> We should get channel impulse response measurements from
> the twinax manufacturers for 10m, 20m and 30m (more if possible)
> including cable+connectors. Is there such a data available ?
> I can run quick simulations in MATLAB, and make them available
> to you. In general, since in the system we are trying to minimize
> number of wires, and at the same time minimize bandwidth + speed,
> that seems to favor multi-level signalling versus NRZ, and I think
> PAM-5 is a good signalling because of the redundancy, it allows including
> control characters, DC balancing, and simple FEC. The reason why one
> would want to include error correction (as Rich has proposed), is to
> relax SNR requirements of the PAM-5 (compared to NRZ), and also to relax
> BER in the PAM-5 slicer (at 2.5GHz or 5GHz, metastability can be a
> challenge for multi-level signals).
> I think in the case of 2up-2down, and maybe 1up-1down (that's
> more of a stretch) CMOS implementation should be possible.
> FYI as a reference, there are 2 papers in the May 98 and May 99
> issues of the IEEE journal of solid state circuits on this:
>  "A 0.4um CMOS 10Gb/s 4-PAM Pre-Emphasis Serial Link Transmitter"
> JSSC, May 99
>  "A 0.5um CMOS 4Gb/s transceiver with data recovery using oversampling"
> JSSC, May 98
> Even though the last paper demonstrates 10Gb/s in CMOS, from our
> experience in high-speed CMOS circuits, anything above 2.5GHz
> is extremely challenging in current CMOS technology (0.25um).
> To the above I would like to add that the equalization work done
> by the HP guys is very promising, and may is a viable technique
> to extended the distance. Is EMC a concern when using pre-emphasis ?
> The ref  also included transmit equalization (3 tap FIR filter).
> Best regards,
Richard Taborek Sr. Tel: 650 210 8800 x101 or 408 370 9233
Principal Architect Fax: 650 940 1898 or 408 374 3645
Transcendata, Inc. Email: rtaborek@xxxxxxxxxxxxxxxx
1029 Corporation Way http://www.transcendata.com
Palo Alto, CA 94303-4305 Alt email: rtaborek@xxxxxxxxxxxxx