|Thread Links||Date Links|
|Thread Prev||Thread Next||Thread Index||Date Prev||Date Next||Date Index|
See also in Annex G which is informative section for how additional information is given for the insertion loss as function of actual temperature vs. requirement at 20degC.
G.2 shows that for measured insertion loss at temperature T, what is the insertion loss at 20degC.
So it looks that it is specified at 20degC, it became worse at higher temperature but designers has to deal with it in their design since all data is available.
So we can implement similar concept for cable and channel resistance vs temperature and as a result for CP2PRUNB vs temperature question.
Moreover, I found there that they assume for 10m minimum cable length. We can use it to. Remember that we agree to test CP2PRUNB also for 0.15m. We can still do it to have this results but for compliance we can use a bit longer cable as part of formal setup. This will help to make PSE PI and PD PI less affecting CP2PRUNB and ease requirements from PD and PSE.
Please check this and share your thoughts.
You may wish to see ANSI/TIA 568-C.2 Annex G for channel length derating at elevated temperature.
CME Consulting, Inc.
Experts in Advanced PHYsical Communications Technology
Can you point on reference showing that channel resistance at 100m specified at 50C?
You may check if you are correct by calculating the resistance at for the cable we use for Type 2 if you are near 25 ohms round loop excluding 4 connector total 0.8 ohms.
I believe that this Ad-hoc should report the worst case cable imbalance at the temperature that creates the worst case condition, and is within the operating range for the ‘channel’. In this case our analysis is including components beyond the PI because we seem collectively to feel it is prudent to do so.
I believe that there is president for worst case analysis including temperature in previous PoE Task Forces. For instance, correct me if I am wrong here but the worst case channel resistance at 100m is specified not at 25C, but rather at a hot ‘edge’ (was it 50C ambient plus cable heating?) In order to guarantee operability between PSEs and PDs, we needed to choose the worst case resistance of the channel. If we want to interoperate, the same principle seems to apply here in my opinion.
I believe that some of the pushback on this issue is perhaps because the worst case imbalance is dominated by the PD diode bridges. These components are indeed not in the PI but we are considering them in this Ad-hoc none the less because they are material to cable imbalance.
Interoperability is a key goal for this and any dot3 standard. I am open to other approaches in achieving this goal as long as it creates confidence in the Task Force and dot3 that component providers and OEMs will understand what they need to do and systems will interoperate.
LINEAR TECHNOLOGY CORPORATION
Please review if I missed your name in the list of attendees on last Thursday a-hoc meeting.
§ David Tremblay / HP
Chief R&D Engineer
Analog Mixed Signal Group
1 Hanagar St., P.O. Box 7220