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Since insertion loss and resistance are proportional the equations will be the same for resistance. I guess this is what you meant correct?
Other question: What is the typical minimum operating temperature of the cables?
I guess patch panels will be near room temperature and horizontal cables could be lower?
The TIA documents give a formula for de-rating the length, when the ambient temperature is above room temperature, similar to the table Alan sent over. Assuming the data center designer follows these formula, the resistance of the maximum length channel will comply with the requirements for the resistance of the 100 m channel at room temperature. Same with resistance unbalance.
Please see what I have found in ANSI/TIA-568-C.2:
Clause 6.4.7 Insertion Loss:
Insertion loss shall be measured for all horizontal cable pairs at 20 ± 3°C or corrected to a temperature of
20 °C using the correction factors specified in this clause. The insertion loss for category 5e, 6, and 6A
UTP horizontal cables shall be adjusted at elevated temperatures using a factor of 0.4 % increase per °C
from 20 °C to 40 °C and 0.6% increase per °C for temperatures from 40 °C to 60 °C. The insertion loss
for category 5e, 6, and 6A screened horizontal cables shall be adjusted at elevated temperatures using a
factor of 0.2% increase per °C from 20 °C to 60 °C. See Annex G for additional information on cable
installation in higher temperature environments.
Horizontal cable insertion loss shall meet or be less than the values determined using the equations
shown in Table 56 for all specified frequencies. In addition, category 6 and 6A horizontal cable insertion
loss shall also be verified at temperatures of 40 ± 3 °C and 60 ± 3 °C and shall meet the requirements of
Table 56 after adjusting for temperature.
I learn from this clause that:
-Insertion loss shall be measured at 20+/-3degC. è Not high temperature as worst case.
-For higher temperature the requirement should be corrected by 0.4%/degC etc.
-Only for CAT6, 6A cables the requirements need verified at 40+/-3degC and 60+/-3degC BUT equation need to be adjusted for temperature by by 0.2%/degC.
As a result this is actually a good example of a parameter that is temperature depended BUT specified at some room temperature e.g. 20, 24degC etc. and correction factors are supplied for the requirement in case of higher temperature.
So If spec is specified at 50deG or at 20degC it is equivalent since there requirements will be correlated by the temperature coefficient of the tested parameter.
This means that the parameter is not necessarily specified at worst case conditions of temperature and all have to meet it even if they don’t work at worst case temperature.
You may wish to see ANSI/TIA 568-C.2 Annex G for channel length derating at elevated temperature.
CME Consulting, Inc.
Experts in Advanced PHYsical Communications Technology
Can you point on reference showing that channel resistance at 100m specified at 50C?
You may check if you are correct by calculating the resistance at for the cable we use for Type 2 if you are near 25 ohms round loop excluding 4 connector total 0.8 ohms.
I believe that this Ad-hoc should report the worst case cable imbalance at the temperature that creates the worst case condition, and is within the operating range for the ‘channel’. In this case our analysis is including components beyond the PI because we seem collectively to feel it is prudent to do so.
I believe that there is president for worst case analysis including temperature in previous PoE Task Forces. For instance, correct me if I am wrong here but the worst case channel resistance at 100m is specified not at 25C, but rather at a hot ‘edge’ (was it 50C ambient plus cable heating?) In order to guarantee operability between PSEs and PDs, we needed to choose the worst case resistance of the channel. If we want to interoperate, the same principle seems to apply here in my opinion.
I believe that some of the pushback on this issue is perhaps because the worst case imbalance is dominated by the PD diode bridges. These components are indeed not in the PI but we are considering them in this Ad-hoc none the less because they are material to cable imbalance.
Interoperability is a key goal for this and any dot3 standard. I am open to other approaches in achieving this goal as long as it creates confidence in the Task Force and dot3 that component providers and OEMs will understand what they need to do and systems will interoperate.
LINEAR TECHNOLOGY CORPORATION
Please review if I missed your name in the list of attendees on last Thursday a-hoc meeting.
§ David Tremblay / HP
Chief R&D Engineer
Analog Mixed Signal Group
1 Hanagar St., P.O. Box 7220