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See inline comments
Some first comments:
2nd bullet. Not clear why you mention SELV etc.?
I think you mean bullet 3. In any case I am talking about the voltage limits at the PI, one of which is SELV voltage so I mention it here
- Try to specify unbalance with absolute values so positive or negative voltage differences is not important.
It is important.
-The fact that lower or higher V2 that can compensate higher/lower R2 is true however the test should address it inherently to simplify the test
The test is no more complicated or simpler. Multiple points need to be taken it is just a matter of the math which is quite easy.
-To cover both points try to define mathematical desired _expression_ and then design what the test setup need to be to test it. For example; I would start to play with the following: RUNB=dV/dI. What is need to be done so for a given requirement of worst case RUNB limit, the dV will not exceed di or equivalent method.
Voltage limits are necessary between the pairs and pairs of pairs. Unless we specify the voltage differences, there is nothing preventing a PSE manufacturer from having one 2P at 50V and one at 57V. If it is allowed there is no way to prevent it. A 7V delta V for each of the 2P outputs will cause a very large current imbalance in your model and in real systems
-I would try to replace the V1 with some fixed resistive load that represents the current during normal operation so P2PRUNB between ANY two pairs can be extracted . (P2PRUNB is defined between any two pairs).
Fixed resistance loads are not enough to specify the PI as explained above
-No need to test pair unbalance. No value added. Its effect on P2PRUNB is negligible.
I do not agree for the reasons stated above.
Here is my proposed way to create balance specifications at the PSE and PI. I welcome any comments.