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I will arrive on Sunday night.
We can talk about that on Monday.
I do agree that the circuits we are using are very similar and so at the end we should get the same results with the same parameters.
The load current in my simulation is indeed swept from low to high for each of the simulation parameter sets shown in my presentation. The negative or ‘reverse’ currents currents would appear between pairs one and three and two and four. The current is flowing in the opposite direction one expects the current to flow. I have run the simulation with a constant power at the PD PI as opposed to constant power at the current load, and just sweeping the current and using spice to calculate the power at the PD PI.
We have been taking a look at the diode. As the dominate term for any reasonable short channel case it is indeed worth putting in the effort to refine it. This is especially true when we add in the diodes for AC Disconnect on the PSE side. It will increase by 50% the current imbalance due to the diode mismatch (to first order).
We have several goals with the simulation, one is to independently verify/validate the maximum current per pair vs. power load (find the worst case conditions for each power level). To do this we need a PSE and PI model to check with and we have come up with a model and calculated the resistor and voltages for the Thevenin circuits for the PSE and the PD, and the very not linear channel.
It would be useful to sit down with you to go over these issues. When do you arrive in San Diego?
The data you can find in the adhoc report and in my presentations come from spice simulations.
The model was presented several times and it is the following:
It is not so different from yours, with the exception due to the PSE voltage mismatch, which I considered to be zero for simplicity.
So the results shouldn’t be so different, and I wish we could converge at the end.
The reason why I never showed negative current is because I used a constant power load, set at two power levels (51W and 75W)
Then I varied the cable length, and reported the results in the table.
I didn’t perform simulation at low load because I assumed that the worst case for the components is at the highest current.
In your simulations you varied the load instead, and at very low load the voltage mismatch were enough to make the current to reverse.
This is due to the diode modeling, which is no more valid but at a single point (e.g at 0.5A). If you look at beia_1_05_14.pdf, page 5, it was clearly stated.
So I think that if you want to simulate the behavior of the end-to-end system varying the load, you cannot use a linearized diode model, since they are not linear.
I hope this helps to clarify the discussion
I am looking at your most recent data presented at the last task force meeting in Norfolk.
Look at your last ad hoc report to the task force in May 2014.
The ad hoc report on page 31 shows that a 2 connector model with 100m as the highest current of 1099.57ma at 75W. The report shows 989.47mA at 0.15m.
At that meeting we openly speculated on how this could be during the question and answer period.
Please look into the negative current. Given the large voltage offsets in this current diode model, there should be negative currents if the simulation is set up properly. The negative current problem was raised in my presentation to the ad hoc.
Here is the circuit I use from my presentation at the ad hoc:
The negative current is the only possible result when you use your simple diode model with very high voltage offsets and low overall resistance which is the case with a short channel. It is simply Ohms law and it is picked up by the simulation. I have never seen the current in all 4 pairs reported in this ad hoc before my simulation results. It would be useful for the group to be able to see the data and sanity check your results.
Again, your math model greatly oversimplifies the problem. Spice is a much better tool for circuit analysis.
1. The possibility of high current at short cable as opposed to the expectation of high current at 100m is known to us from our work on July 2013 and adhoc meeting and February 2013 from the analytical analysis. It depends on End to End Channel P2PRUNB and the absolute resistance of each component in the system. Please see Annex B from adhoc material attached below with simulations that confirmed it.
In Short it depends on the following:
2. In Christian and my work a year ago, We checked results at channel <=1m and 100m with the database components at that time and I got higher current at 1m.
3. If your PSE PI and PD PI unbalance is very high, yes, you should expect to much higher current at the short channel as expected by the system equation and confirmed in simulation.
4. Regarding negative current. I don’t remember that I saw something similar. Not clear to me how it can be?, can you send the spice drawing to check if there are issues with the model?
The following is per older data base, 4 connector channel model with PSE and PD PI.
The following is per older data base, 6 connector channel model with PSE and PD PI.
This is some interesting data, with the current set of assumptions using my PI definitions and Wayne’s channel, Wayne A is the problem child for maximum pair current. It should be noted that the current diode model cause negative current to flow on both the high side and low side pairs. I believe we need to address this diode model.
Yair and Christian,
Did you not see negative current in your simulations on either the high side or low side pairs?
It seems to me, you are trying to solve two problems:
- You want to know the absolute worst case cabling pair-to-pair DC resistance unbalance
- You want to know what the unbalance actually is, more accurately than the worst case.
I think the proposal in red addresses the first problem.
For the second problem, I think you can use the four use cases I proposed, and the values of the cabling components I provided, or others you think are right. You can add more use cases, but you should not add unreasonable ones.
I need the 0.1 ohm, since this is the correct number and it gives me better channel unbalance.
I need the 0.2 ohm to address your use case #2 which is valid use case but yet crosses the 7%.
I need explicit text that will prevent me to argue with future test house when they may use unrealistic channel installations.
What I offer is covering what your are proposing but not the opposite.
Why not just,
The maximum DC resistance unbalance between pairs of a channel shall not exceed 0.200 Ohms or 7 %, whichever is greater.
That would avoid lengthy sentence about ignoring it when the resistance is less than .200 Ohms.
Hi Wayne and all,
Please see slide below from my presentation on Tuesday adhoc which addresses your question.
You can see ,as expected, the peaks of the "nonrealistic use cases" and one realistic use case B are happens when channel Resistance difference is below 0.2 ohm.
Also consider the fact that the connectors that I have use in the simulations are with Rmin=30 miliOhm and Rmax=50miliOm which means Rdiff=80miliom max for 4 connectors or 40miliokms for 2 connectors etc. which you can see from the plot that the peaks of the "nonrealistic use cases" is below 40 miliOhm or so for <=2 connectors.
Now what I thought to do with it is to have a text saying that:
I am proposing the following text to fix all issues:
The Channel P2PRUNB shall not acceded 7% or maximum pair to pair resistance difference of 0.1 ohm whichever is greater.
Channel P2PRUNB of a channel with maximum pair to pair resistance difference of 0.2 ohm may be ignored.
(Or instead of "may be ignored", shall be limited to 25% max. (25% max is the mathematically upper bound of P2PRUNB of any number of connectors with zero cables with the parameters we used)
I'll appreciate, any comments on this.
Would the existence of a spec, such as, not more than the max of .2 Ohms (or .1 Ohms) or 7% (or 6%) achieve this closure?
Wayne I agree that we shouldn't be worried about.
The question is how to convert "don’t worry it is unrealistic in real installations" to "don’t worry, the spec says A, B, C" therefore don’t worry.
I am looking for some text/other means to close this hole in the future spec so if someone during tests will have "unrealistic channel" that is used in the lab and not in real life installation I can point him to the spec and say "this is wrong setup ..and this is why, see the spec." .
I am working on such closure.
My opinion would be that the unrealistic use cases do not need to be worried about.
This solution, filters the "unrealistic use cases" that were resulted from short cables.
How it helps?
If we set a limit for the channel for 7%, and a user did use cabling and connectors combinations that is considered "not typical use case" or even "not realistic use case" and he got 12% it will be an issue for him. The spec says A and he got B.
This filters all the results of B which are not relevant to him when the channel is tested as standalone part.
The justification for this approach is, when the channel is connected to a system, and the channel uses short cables, the End to End current/resistance unbalance will be dominant since their unbalance is higher than the channel.
This is one of the solutions from the table.
There is 5th solution that in after our adhoc meeting Sterling and I were discussing and I am working on its details.
You showed a spreadsheet of four possible solutions, and one of them was to measure the DC resistance unbalance of the cabling channel with resistors in series with it.
What is the problem these solutions are solving?
Your question Is not clear to me can you elaborate?
I was trying to ask, what problem is being solved by this?
Please announce when and why the ‘formal meeting’ has ended in the future.
I meant that we continue to discuss after the time of the forma meeting. The formal meeting ends when there is not sufficient attendees or someone ask to finish on time, or most of the group agrees to continue, so after that time we can continue discussion whit out having decisions.
What do you mean by formal ad hoc meeting?
I am working on this direction too and few others that we discuss after the formal 1 hour time of the adhoc meeting.
The entire principle of adding balanced resistance to test imbalanced channel resistance does not represent any real system. PSE PI and PD PI will add imbalance in worst case analysis. At the end of the day only full worst case analysis using all three components will give us the correct worst case maximum current