Re: [802.3_4PPOE] Open Circuit Vdiff Test
Ok on all points, thanks for your feedback,
On 1/22/2015 10:32 AM, Darshan, Yair wrote:
Many thanks for your comments.
We did address your concerns and my response to the current motion that passes for PSE Vdiff=2mV maximum is the following:
1. I also got ~10mV to 30mV range of Vdiff when you have separate two diodes over each pair-set for AC disconnect.
2. Users that want to continue using AC disconnect can implement it with a single diode for both pairs set so Vdiff=0.
Other issues that those users need to be aware is the power dissipation especially in Type 4 applications.
3. Defiantly PSE Vdiff=2mV force PSE designers to use AC disconnect per (2) or not use it at all.
4. System wise, we cannot afford PSE Vdiff to much higher than 2mV due to its huge effect on unbalance at low current and short cable together with PD Vdiff. We choose to limit PSE Vdiff to a minimum possible and allow higher PD Vdiff where it is more needed to allow cost effective PD design using Schottkey diodes.
From: Ken [mailto:ken_bennett@xxxxxxxxx]
Sent: Wednesday, January 21, 2015 3:10 PM
To: Darshan, Yair; STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: Open Circuit Vdiff Test
Hi Yair, All,
I've attached a simulation of a Vdiff open circuit measurement which shows a 20mV Vdiff result for an internal current leakage difference of 10uA. The implication is that a series forward-biased diode feeding the PI can easily fail this conformance test unless it feeds both pairs of the same polarity through a common node.
Avoiding any forward-biased diodes which feed a single pair in 4-pair PSE designs may be the only practical means to consistently avoid this test failure. This would likewise result in better balance at high currents. However, some AC MPS and protection methods may be impacted by this, so a note in an Annex and perhaps removal of AC MPS in 4-pair designs might be warranted.
The above points probably do validate the omission of such PSE diodes from 4pr unbalance models, which is helpful.