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This is a tricky problem thanks for tackling it.
As I was not in the room when this got discussed I’m very likely missing some detail on the problem you are trying to solve. This may be a benefit as I am just reading what is being proposed as a PD designer that was not ‘in the room’. For instance I am not sure where you were planning on inserting the new text. Sans that context your proposed wording may run into a problem of interpretation which could make existing compliant PDs non-compliant.
PDs shall not draw more than the maximum current allowed by a PSE during inrush as outlined in section 220.127.116.11"
One valid reading of the proposed text could be that the PD must always stay under the PSE current limit during inrush. Many PDs let the PSE handle the current limit during inrush which is currently allowed.
I’m just guessing but is it the case that the turning on of the PD load causes the PSE to go back into current limit (after the PD has reached 99% of its final value)? This could cause the PSE to go back into current limit and ‘fold back’ the voltage, which can cause the voltage at the PI to go below the Voff voltage.
We have seen PDs that quickly charge up small capacitors, then turn on a load with no soft-start and expect the PSE just to deal with the consequences including the negative resistance of a DC to DC converter. Depending on how the PSE has implemented Ilimit and foldback, it sometimes worked and sometimes did not.
If this is the case, maybe stating it explicitly would help.
“After the voltage at the PD PI has reached 99% of its final value, the PD shall stay under the minimum PSE current limit as defined by…”
BTW, the existing language of “Cport is charged 99% of its final value” has always been a bit troubling to me because the PD may not be know what the final value is, and Cport is an internal component not testable at the PD PI. As far as I know the PSE is allowed to change its final voltage during inrush for instance. I do NOT think there are problems in the field with this pedantic reading of the specification but it is kind of unclear. If we are touching this, maybe we could think about referencing the PD PI for instance instead of an internal capacitor. This is why I included PD PI language in my suggested text.
In Jan interim meeting, Jean and I presented about clarifying PD load turn on behavior that will help in making sure non-compliant behaviors are avoided. The team directed us to submit this as a maintenance request. Here is what we are planning on submitting – given the maintenance request will come back to 4PPoE group, we would appreciate any comment from 4PPoE group before we submit it.
- PDs in the field turn on their Load during Inrush. This leads to PD cap not charging up fully (even if C<180uf and PSE is following inrush rules from 18.104.22.168). This may lead to operational problems after inrush. There is a Voff requirement in PD table 33-18 to ensure power supply remains turned off for V<30V, but customers seem to read this as applicable only "after power on" not during "power on" - hence they turn on their DC-DC during inrush causing problems.
Add the following to section 22.214.171.124
"PDs shall not draw more than the maximum current allowed by a PSE during inrush as outlined in section 126.96.36.199"
Add the following to section 188.8.131.52 at the end of second paragraph.
"The turn off voltage Voff applies both during power on and after power on"