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I think Yair is the person that has reviewed this the most.
It takes time to turn on two hot-swap paths that may be in two separate ICs that are not synchronized. Roughly speaking it takes 10 I2C transfers per setup so a delay of about this 10 transfers x 10b/transfer x 10 us/bit = 1ms is expected. The controller may also take time to process the request so add some more time. The controller has about 2 ms to reach 0.6A before the second controller kicks in. This is probably conservative but acceptable. This is a pairset-2-pairset unbalance and should not corrupt the Ethernet transfer, which probably has not started any way.
I do not see this as a problem.
All, while reviewing the spec I noticed these numbers in Table 145-28 (PD power supply table):
Single-signature PD, Class 7 to 8 IInrush_PD 0.8A
Single-signature PD, Class 7 to 8 IInrush_PD-2P 0.6A
And this in the text portion (184.108.40.206): PDs shall draw less than IInrush_PD and IInrush_PD-2P from TInrush_PD max until Tdelay-2P min
This means that the PD can only draw 800mA max on inrush but that it could be 600mA on one pairset and 200mA on the other. This is an immense amount of imbalance – more than a PD is allowed to have. Why do we have such a large allowance on inrush?
Tech Lead, Cisco Systems
Chair, IEEE P802.3bt 4PPoE Task Force