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For DS, Sequence 3 enforces that detection on secondary pairset does not occur until after the primary pairset is powered. That is what is meant by “staggered”. For DS, Sequence 0, the detection/class has no enforced timing relationship. “Parallel” just means that they happen pseudo-concurrently, but not necessarily sync’d.
From: Lennart Yseboodt [mailto:lennartyseboodt@GMAIL.
Sent: Friday, September 01, 2017 4:04 AM
Subject: Re: [802.3_4PPOE] PSE state machine - Stuck in ENTRY_SEC and related issues.
Question to the folks who came up with the various CC_DET_SEQs.... what was the design intent of sequence 3 ?
I have the feeling there is a difference in interpretation of what is meant by "staggered" and "parallel".
For sequence 0, it is stated that "Connection Check is followed by staggered detection for a single-signature PD and parallel detection for a dual-signature PD."
Does 'parallel detection' imply that the detection has to happen precisely at the same time ?
Or can you do detect on pri, then detect on sec, and then proceed to classification ?
I would assert that the latter behavior is allowed by the state diagram.
Even if do_detect_pri and do_detect_sec are called at the same time, nothing forbids one of these functions to wait a bit until the other is done.
On Fri, Sep 1, 2017 at 3:10 AM, Heath Stewart <00000855853231d4-dmarc-
Thanks for your presentation. There are some interesting issues you identify in comments 251 and 252. We have reflected on your proposal and have created a proposal to address these issues.
On Thu, Aug 31, 2017 at 3:12 AM, Yair Darshan <YDarshan@xxxxxxxxxxxxx> wrote:
Please review the remedy for this topic.
It handles the following:
1) Preventing to be stuck in ENTRY_SEC when detection in primary has failed or tdet_timer_pri is done when transitioning from ENTRY_SEC to
2) The transition from IDLE_SEC to START_DETECT_SEC when CC_DET_SEQ=3 is not fully covered for the staggered detection timing range.
3) Both (1and 2) prevents doing cycles of detection and classifications until host decides to power on the port.
I’ll appreciate your inputs.
Chief R&D Engineer
Analog Mixed Signal Group
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