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Re: [802.3_4PPOE] Concurrency issues in the PSE state diagram

Hi Yair,

Thanks for reviewing. For this particular issue it is only the top level and SISM state diagrams that are in conflict.
I listed all of the PSE state diagrams as a reminder that any combination can lead to concurrency issues, but that is indeed a bit beside the point.

Kind regards,


On Sun, 2017-10-29 at 11:06 +0000, Yair Darshan wrote:
Hi Lennart,
For that particular states (ENTRY_PRI and ENRY_SEC), I see that you add a state so the content of ENRY_PRI/SEC will not be changed when sism=FALSE which allow access to ENRY_PRI/SEC and cause issues with sig_pri/sec. So far this is OK. It is not clear to me how this relates to rest of the state machines you have mentioned?
Figure 145-13 The top level
- Figure 145-14 PSE Autoclass
- Figure 145-17 MPS (tmpdo timer)
- Figure 145-18 The Primary and Secondary MPS (tmpdo timer pri and sec)
- Figure 145-19 The inrush monitors (Primary and Secondary), slated for removal 

-----Original Message-----
From: Lennart Yseboodt [mailto:lennartyseboodt@xxxxxxxxx] 
Sent: Friday, October 27, 2017 2:52 PM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: [802.3_4PPOE] Concurrency issues in the PSE state diagram


Hi all,

There are concurrency issues in the SISM PSE state diagram.
Attached my fix.

Kind regards,


Lennart Yseboodt <lennartyseboodt@xxxxxxxxx>