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Re: [802.3_4PPOE] PD Transients (yseboodt_04)

Hi Lennart and Ken,


I think the easiest way to solve this is to take the reference when the transient voltage is complete (Vpse constant and out-of-current limit).

As this is the only reference point for which all simulated Pclass_PD and Cport combinations pass.


For interoperability, it might indeed be better to add the requirement to the TR1 and TR2 that the PD may not force the PSE to be current limited to IIim,min more than Tlim,min.



In principle I’m not against Ken’s suggestion to increase Ttransient and take another reference point.

I only fear this could lead to a longer discussions.

If we still want to take this path then I would suggest deducing the values from the following constraints:

1.      From the AC power waveform, define the Transient Energy = (Ppeak_PD – Pclass_PD)*Tlim,min

and apply this to the Cport: ½ Cport (Vfinal^2 – Vinit^2).

This gives one maximum value Cport

2.      The requirement that the PSE may not to be current limited to IIim,min more than Tlim,min gives another maximum value for Cport

Take the minimum of both Cport values and define based on this capacitance the time the PD may exceed Ppeak_PD or Ppeak_PD-2P.



Best Regards,





From: Ken [mailto:ken_bennett@xxxxxxxxx]
Sent: Wednesday, November 01, 2017 3:58 PM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_4PPOE] PD Transients (yseboodt_04)


Hi Lennart,

If there's currently no interoperability issue for 180uF and 360uF, then selection of the starting point only places a burden on the PD with respect to the test.  It's not clear to me that the test accurately reflects what a PSE will allow before shutting down, but in any case, I thought starting Ttransient at the conclusion of the step might have changed the test from its initial intent and simulations.  If actual interoperability is unaffected by it, then selecting the end of the step is ok, however I would suggest increasing Ttransient rather than starting it at the end of the step, to avoid ambiguity with respect to current limiting at the source.

Best Regards,



On 11/1/2017 10:15 AM, Lennart Yseboodt wrote:

Hi Ken,


I checked the simulations.

With the reference taken as when the system goes into a current limiting mode, at least Class 8 and Class 4 flip from OK to failing the transient requirement (with a 360uF and 180uF cap respectively).

Other Classes may also be affected, I didn't check.


While I also am glad to see the "intrinsically OK" text gone, it should be our goal to make it such that PDs with capacitors of 180uF and 360uF do not need special provision to deal with transients.

That is after all the basis on which TLIM and ILIM have been chosen.


Given that there is no interoperability issue with the reference taken when the voltage transient is complete, I fail to see why we should increase the burden on the PD ?


Kind regards,




On Wed, 2017-11-01 at 09:48 -0400, Ken wrote:

Hi Lennart,

The TR1,2 are steps with a rise-time, however they are also described as having a current limit.  If the source current limiting kicks in, then the end of the transient doesn't occur until the limiting ceases.  The easiest reference is the beginning of the transient because there are no ambiguities. 

I think this was the intent early-on, however as you point out, the rules aren't clear, and neither are the origins (at least in a quick search).  The existing text doesn't explicitly reference the beginning:

During a transient the input power of the PD may exceed PPeak_PD or PPeak_PD-2P. Table 145–30 defines
three PSE output voltage transients.

When transient TR1 or TR2 is applied, the PD shall meet the operating power limits after TTransient as
defined in Table 145.

However If the intent was to reference the end of the transient, I would think the second sentence would have been:

AFTER transient TR1 or TR2 is applied, the PD shall meet the operating power limits after TTransient as
defined in Table 145.

In any case, the TR1,2 test requirements are an extreme corner case and there's no longer any suggestion to the reader that specific capacitances will "intrinsically" pass, so I don't see a problem with the reference being at the beginning. 

Best Regards,



On 11/1/2017 8:29 AM, Lennart Yseboodt wrote:

Hi Ken,


The PD not spending more than 6ms or 10ms in the current-controlled mode is also something the PD should meet.

We currently do not have a requirement for this (ie. it is possible to meet TR1/TR2 but spend more than TLIM in the input current mode).

Note that all Class/Type combinations currently do not violate TLIM.


The current text does not offer a reference for Ttransient. I picked the end of the source transient because it is an easy to find point.

If we shift the reference point backward in time, the PD margin decreases and we may have to increase ILIM to TLIM to make things work again.


- Should we add a requirement to the TR1 and TR2 that the PD may not be current limited to ILIM for more than TLIM ?

- Given that currently there is no issue with TLIM, do you still feel we should move the reference point back ?


Kind regards,




On Mon, 2017-10-30 at 09:39 -0400, Ken wrote:

Hi Lennart,
The new text:  "referenced from when the ‘final voltage’ is reached at 
the source", sets a time boundary which is after the time that the PD 
starts to violate Ppeak_PD.  Seems like it should start at the beginning 
of the transient, so that the PD Peak excursions that are beyond 
Ppeak_PD are no wider than 10ms and 6ms, to match Tlim_min in the PSE 
Best Regards,
On 10/29/2017 10:09 AM, Lennart Yseboodt wrote:
Hi folks,
Attached proposed baseline for the PD transients section.
At the September meeting it became obvious that Table 145-30 wasn't 
terribly clear.
I've re-simulated all of the transient conditions and, except for 
Class 7, everything is OK.
We may want to consider increasing the ILIM for Class 3, Class 4, and 
Class 8 to make it such that PD's that "intrinsically" should be fine 
actually are.
See simulation_annot.pdf for simulation results.
Kind regards,