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for the meeting that we have today at 16:00 CET, I would like to ask the Task Force to
consider a late comment against P802.3bv/D3.2 from my side.
It would be useful that the bit 3.519.10, PHD lock status, is latch low (LL), because the PHD is used for
communication between state diagrams and for the OAM messages passing. Doing this bit LL would
allow the user to know in any case when happens the condition rcvr_hdr_lock = NOT_OK.
Use case: the link_status = OK is not reached because the PAM16 payload data reception is not
reliable, but the quality may be enough for PHD and hence OAM message passing. According to http://www.ieee802.org/3/bv/public/Mar_2015/perezaranda_3bv_3b_0315.pdf
the margin of PHD wrt payload sensitivity is 10 dB. Specially useful in automotive applications.
Change column R/W, row 3.519.10, of Table 45-160d from “RO" to “RO, LL”.
Add in pg 32, line 20:
"Bit 3.519.10 shall have latching low behavior.”
Move the PICS numbers RM150 to RM156 to become RM151 to RM157.
Add new PICS item to Clause 45, as:
"RM150 | PHD lock status behavior | 220.127.116.11d.6 | Bit 3.519.10 has latching low behavior | PCS:M | Yes [ ] N/A [ ] “
Thank you and best regards,
802.3bv Editor / Comment Editor