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RE: [10GBASE-CX4] Xmt Level




Steve, we do not see a problem with 800mVp-p differential at 130nm using no
special tricks or transistor construction.   Our 130nm process is pretty
generic so I would suggest that the issue is not the amplitude.  

I would prefer to leave the xmt amplitudes as is.  

BTW, most, if not all, 130nm processes require multiple supplies for
backward I/O compatibility, so the point of adjusting this spec to allow a
single supply device is not valid.  I'd like to have a single supply device
too, but the fact remains that I/O voltage levels always lag process
technology.  This dictates a world of where IC's have multiple supplies.   

Regards,
Shawn

____________________________________________
Shawn Rogers,   PMP               s-rogers@ti.com
High Speed Serial Link Marketing
Texas Instruments
12500 TI Boulevard / M/S 8732/ Dallas, Texas 75243
Office: 214.480.2678                        Cell: 214.549.4868
______________________________________
 

-----Original Message-----
From: Dreyer, Steve [mailto:steve.dreyer@intel.com] 
Sent: Friday, January 03, 2003 10:15 AM
To: stds-802-3-10GBCX4@ieee.org
Subject: RE: [10GBASE-CX4] Xmt Level


Howard,

The process you are using is probably different than ours,
that is why we get different results.   But  we have seen 
800mV being difficult to impossible on on 2 different processes.
So, I would make the claim that it is a real issue that others
could experience as well.  

And lowering the amplitude by 50mV is not that big a deal for the
receiver.

Using thick ox devices is not a very good solution because
it requires a higher supply, which means more power, and now the
IC requires dual power supplies.  

Our customers want a single 1.2V supply and low power.  I think if 
lowering the level by 50mV can make this achievable  by everyone, 
that is a big plus.

Steve



> -----Original Message-----
> From: Howard A. Baumer [mailto:hbaumer@broadcom.com] 
> Sent: Friday, January 03, 2003 8:08 AM
> To: Dreyer, Steve
> Cc: stds-802-3-10GBCX4@ieee.org
> Subject: Re: [10GBASE-CX4] Xmt Level
> 
> 
> Steve,
> 	There areexisting 130nm parts that put out > 800mVppd.  
> Our simulations
> for our designs shows that this is possible.  For the 90nm process a
> designer can use the higher voltage fets to achieve even a 1 or 1.2V
> output.  Yes these fets are slower than the stnadard fets of 90nm but
> they will be faster than the stnadard fets for 130nm.
> 
> 
> Howard
> 
> 
> "Dreyer, Steve" wrote:
> > 
> > Howard,
> > 
> > My comment to your comment to my comment below.
> > 
> > Steve
> > 
> > > "Dreyer, Steve" wrote:
> > > >
> > > > Howard,
> > > >
> > > > Took a quick look at the proposed draft and have the following
> > > > top level comments:
> > > >
> > > > 1. The min xmt amplitude of 800mV is probably not doable on a
> > > >    chip with 1.2V only supply when all worst case conditions are
> > > >    considered, it probably needs to be dropped another 50mV
> > > >    or so.  I plan to have a quick presentation showing
> > > >    this next week.  For reference, the min XAUI level is
> > > >    a lot lower than 800mV using the far end method.
> > >
> > > <HAB>
> > >       The 800mVpp is for a differential signal so that is
> > > only a 400mV single
> > > ended swing at the driver output, this is attainable with a 1.2V
> > > supply.  Also the 800mVpp min is not the minimum the driver
> > > puts out, it
> > > is the minimum for the lower limit of the peak in the 
> transmit output
> > > template you reference in #3 below.  This will have to be
> > > clearified in
> > > the text.
> > > <HAB>
> > >
> > 
> > <SD>
> > Our simulations show that 800mV dif pp (or 400mV single ended) can't
> > be done at 1.2V when worst case conditions are put in 
> place.  We have
> > simulated with both a 130nm and 90nm process.
> > 
> > Propose we reduce the min level a bit based on these simulation to
> > maybe 750mV (will have exact number next week).
> > 
> > The 750mV is still larger than current XAUI min (if far
> > end spec is used), and reducing xmt level by 50mV reduces receive
> > sensitivity by 5mV, not a big impact on receive.
> > 
> > I plan to show simulation  results next week at Vancouver.  Maybe we
> > should wait until then to discuss further.
> > 
> > Steve
>