This is good dialog and is representative of the communication we will
need to have with the public regarding how we got to where we are and why
it is the right thing. Some points...
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Ethernet provides substantial value to the industry by making large functionality
steps and challenging the technology suppliers to deliver them. The
1G to 10G transition is this type of step. Incremental, 2x steps
tend to slow down the industry's forward implementation leaps.
-
The project objective is to do 10Gbps; and we are trying to do that on
as much of the existing infrastructure as possible. The project objective
was not to do whatever speed we can on the existing infrastructure.
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While there was significant discussion early on regarding esoteric materials
and costly manufacturing techniques, there have been a number of significant
developments: The significance of loss and materials in 10G backplane
construction has diminished. The group has come to realize that design
techniques (stubs) have a much larger detrimental effect than board material
selection (loss). The implication is that basic, good design and
manufacturing can avoid the use of exotic materials, particularly for channels
less than 35 inches. This distance easily encompasses the vast majority
of the volume market.
-
As evidence of the feasibility of operating on lower grade materials than
the project objective: 10Gbps performance on FR-4 grade materials greater
than 1m in length has been demonstrated using existing silicon. The
material is the lowest grade capable of mandatory no-lead solder manufacturing
requirements. The silicon is more basic than what will be available
for the 802.3ap standard.
http://ieee802.org/3/ap/public/mar05/oganessyan_01_0305.pdf
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3. The backdrilling manufacturing operation has been demonstrated by two
independent groups to be a very minor cost adder.
http://ieee802.org/3/bladesg/public/mar04/oltmanns_01_0304.pdf
http://ieee802.org/3/bladesg/public/mar04/dambrosia_01_0304.pdf
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NRZ signaling has been incorrectly cited by (below) as the cause of having
to backdrill or use higher grade materials. This is not correct.
NRZ performed better than any of the other available signaling methods.
The use of other signaling methods would have limited the serve-able channels
even more. The cause of any improvement in channels is the need to
drive 10Gbps, no matter what the signaling method.
http://ieee802.org/3/ap/public/mar05/liu_01_0305.pdf
http://ieee802.org/3/ap/public/mar05/altmann_02_0305.pdf
http://ieee802.org/3/ap/public/mar05/brink_01_0305.pdf
http://ieee802.org/3/ap/public/mar05/anderson_01_0305.pdf
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The project continues to pursue serving even the worst, non-backdrilled
channels, using the most qualified signaling available.
http://ieee802.org/3/ap/public/mar05/seemann_01_0305.pdf
Brian
Reuven Segev wrote:
I
tend to agree with Jia. We heard from many system vendors that they are
interested to design 20G and 40G line cards. In these cases, cutting the
number of backplane traces by 2X is essential and, as Jia point out, not
having to use esoteric materials and costly manufacturing techniques as
required by 10G SERDES results in a substantial economic benefit.Regards,
Reuven
Reuven
Segev
Director
of Marketing
TeraChip,
Inc.
Tel:
(650)320-8148 ext 204
Cell:
(415)307-7683
Hello everyone, As a new designed backplane
for 10GBASE-KR, maybe its economical, however for 1000BASE-KX and 1000BASE-KX4
application, it must be expensive. The only advantage is that it is compatible
with 10GBASE-KR. As for 6.25G interface, I personally
think it is necessary for IEEE 802.3 ap to cover it. According to our analsysis
through simulation and meausrement, systems for 2.5/3.125 Gbps application
can be easily upgraded to 5/6.25 Gbps,given the backplane design be slightly
changed. We can even use common FR4 instead of improved FR4. However, there
lies in great difficulties for 2.5/3.125 systems to be upgraded to serial
10Gbps. Jia Gongxian
Huawei Technologies Co.,Ltd.
Tel: 86 755 89651154
FAX: 86 755 89650731
Email: jgxian@huawei.com
website: http://www.huawei.com
----- Original Message -----
Sent: Friday, March 18,
2005 12:52 PM
Subject: Re: [BP] Opinion
about the Channel Model Ad Hoc
Interesting
post.Brings
forward the question on whether there is economic justification for the
10G per lane, given the incremental cost incurred by the backplane and
the line cards. Any comments/opinions? An
additional question would be the reason for not including a 6.25Gx 2 lanes
solution. After all, the OIF does have a specification for a 6.25G interface.
What would be the PCB (backplane and line card) trade off for 3.125, 6.25,
10?I
would be curious to learn more about that.
Reuven
Reuven
Segev
Director
of Marketing
TeraChip,
Inc.
Tel:
(650)320-8148 ext 204
Cell:
(415)307-7683
Hi
all IEEE P802.3ap Task Force Members,I
have been concerned for IEEEE 802.3 ap Task Force for a long time,
and have read through all the relevant materials available from the website
up to now. I do hope I have a chance to discuss with all members
about the project as a system backplane designer, to share what I
think about it. Since it is inconvenient for us to take part in the face
to face meeting and teleconference, I hope I can use the "e-mail reflector"
as a platform to share with you all. The
following is what I want to know and what I care about most:1)
From the object objective, the project will cover
1 G per lane, 3.125 GbpsX4 lanes and 10Gbps per lane. Does this mean
the channel will meet all the scope at the same time ? For
the legacy backplane used for around 1 Gpbs , most of them is made of common
FR4 and general connector,such as 2mm connector without shield pin.
I think it is very hard to upgrade to serial 10 Gbps, at most up to 3.125
Gbps, economically.For
the legacy backplane used for around 3.125Gbps per channel,
we still use common FR4, not improved FR4, and apply common manufacturing
technology.For
the NRZ coding 10Gbps application, if we use this kind for backplane, I
think this is very hard to realize. Thus I think for serial 10G backplane,
we may using Greenfield backplane, not legacy backplane.According
to our simulation and measurement results, the insertion loss of
channel up to 3 GHz or so, is mainly effected by attenuation of copper
loss and dielectric, impedance discontinuity caused by trace and connector,
beyond 3 GHz, the via stub play a more and more important role, firstly,
backplane via stub, secondly, line card stub. Given
we want each layer in PCB can be routed high speed signals,for NRZ coding
5/6 G application, backplane via maybe need be backdirlled, for NRZ coding
10 G application, line card via maybe backdrilled also.Does
this project plan to using common PCB technology to make the backplane
and linecard ? or using backdirlling and other technologies to reduce the
via stub ?2)
As for the channel model, I think the channel specifications from TP1 to
TP5 is important, especially for 10G serial application. for 1G per lane
and 3.125G X 4 lanes application, maybe we can ignore the influence
caused by the component from TP4 to TP5 (two line card vias and a compactor),
since before 3G Hz, the via's influence is limited, however, for 10G serial
application, especially for NRZ coding, line card vias also play a great
role for the channel performance. According to our simulation result, for
the via routing in layer 2 (line card is about 2.5mm thick), beyond 5 GHz,
the insertion loss of the via drop's sharply. We need define specifications
from TP1 to TP5, instead of the specification form TP1 to TP4. 3)
As for the test sample, I think we should define some specifications
to guide how to design. The test samples must actually reflect the real
product design, or else, the measurement result and conclusion according
to the result is meaningless. For example, different types
of test launches we used will greatly influence our test result.
I think the rules is, the design will reflect the practical design, not
just for test. For instance, we can use optimized SMT sma and with
a PTH (plated through hole) with 8/10 mil diameter to reflect the BGA via
in practice.4)
As for the channel crosstalk, some member have mentioned using power
sum to define the spec, however, the project is aim at high speed digital
application, all the standards are defined as voltage in practice, such
as eye height, imput sensitivity, ect. We usually using voltage sum to
calculate the worst case of crosstalk, not power sum. 5)As
for the Serdes, It's better to integrated ac compactor into Serdes,
which will significantly improve the channels performance, for we can reduce
2 line card vias and a compactor in linecard.
Serdes for 10G serial applications must have adaptive equalization
and BIST function.Any
comments will be welcomed.Thanks
and Best regards.Jia
Gongxian
Huawei Technologies Co.,Ltd.Shenzhen China Tel:
86 755 89651154
FAX: 86 755 89650731
Email: jgxian@huawei.com
website: http://www.huawei.com
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