Re: [BP] DC block capacitors in 10G NRZ channels
Hi Steve,
Regarding your first point, yes, if the DC block is located after the 50
ohm termination and the clamp diodes, then the clamp voltage cannot be
set independently of the TX DC bias. In particular the clamp voltage can
no longer easily be set such as to allow equal excursions of the signal
in both directions from its bias point. This is definitely a limitation
to be considered. The RX can of course still be biased in its sweet
spot, independently of the TX bias.
Regarding your second point, I understand your concern about having two
resistors where you only had one, and that each resistor (and for that
matter also the DC block capacitor) will have some capacitance to GND
and potentially negatively affect the return loss. My belief is that the
additional capacitance can be small (compared to main contributors such
as clamp diode capacitance) but I am not a SERDES designer and would
prefer to hear from one. However I would claim that any such
degradation is much less than that due to having to introduce an
external DC block in the signal path.
Vicente
-----Original Message-----
From: Steve Waldstein [mailto:Steve.Waldstein@TUNDRA.COM]
Sent: Monday, June 05, 2006 2:05 PM
To: STDS-802-3-BLADE@listserv.ieee.org
Subject: Re: [BP] DC block capacitors in 10G NRZ channels
Vincente and Brian,
I am new to this reflector so please excuse me if this has been brought
up before.
I support allowing the implementer to determine where the DC clock
capacitor is but isn't it important to ensure that the implementation of
the termination does not limit the signal swing at the receiver? If the
capacitor comes after the termination then the common mode point of the
termination effects the allowed swing. If the termination is on-die and
common mode point is ground, like in PCIexpress, then the single ended
swing is limited by the clamping diodes of the technology. The
implementer will have to ensure that the clamp can not turn on if the
maximum swing arrives at the receiver. Will this be a problem in this
configuration?
Also, this kind of configuration, with the capacitors after the
termination, typically increase the receiver capacitance since you have
the parasitic capacitance of the termination and then the parasitic
capacitance of the network setting the common mode point of the receiver
after the DC blocking capacitor. This creates another type of it
challenge on meeting any reasonable return loss requirements.
Steve Waldstein
Tundra Semiconductor Corporation
39 Darling Avenue
South Portland, ME 04106
Voice: (207) 773-2662 x3047
FAX: (207) 773-1550
E-mail: steve.waldstein@tundra.com <mailto:steve.waldstein@tundra.com>
-----Original Message-----
From: Cavanna, Vicente Vaca (Sr. ; ProCurve ASICs)
[mailto:vicente.cavanna@hp.com]
Sent: Monday, June 05, 2006 3:09 PM
To: STDS-802-3-BLADE@listserv.ieee.org
Subject: Re: [BP] DC block capacitors in 10G NRZ channels
Hi Charles,
I agree with Brian that the spec should not preclude internal DC blocks
(if indeed it does).
It does not seem unreasonable (in regards to the concerns you raised
about size and offset voltage) to integrate a 10pF capacitor and a 5K
bias resistor to obtain a 50ns time constant. Such a time constant would
be adequate for an 8B/10B code (even at 1 Gbps) or for other codes
whose disparity is better bounded than for the 64B/66B code.
Such a SERDES with integrated DC block capacitor, unless it had some
means to bypass the DC block or to comensate for baseline wander, would
not be suitable for 64B/66B codes, but would be very attractive for many
other applications.
Vicente
-----Original Message-----
From: Brian Brunn [mailto:brian.brunn@XILINX.COM]
Sent: Monday, June 05, 2006 8:38 AM
To: STDS-802-3-BLADE@listserv.ieee.org
Subject: Re: [BP] DC block capacitors in 10G NRZ channels
Hi Charles,
While putting the AC coupling capacitor on chip is 'not really that
easy', we want to make sure we do not preclude it. Especially since we
are not limited to just passive components to realize these functions.
In that vein, the best choice for putting the AC coupling capacitor on
chip may involve putting the cap AFTER the termination (the
configuration Vincente describes).
So the standard needs to be clear that putting the AC coupling capacitor
after the termination is allowed and that for system designers, there
may be DC current flowing through the termination resistors. Up until
know, the description of AC coupling appears to be incomplete.
Brian
-----Original Message-----
From: Charles Moore [mailto:charles.moore@avagotech.com]
Sent: Friday, June 02, 2006 12:07 PM
To: STDS-802-3-BLADE@listserv.ieee.org
Subject: Re: [BP] DC block capacitors in 10G NRZ channels
While i recognize that putting the AC coupling capacitor on chip would
be desirable it is not really that easy.
The 100nF off chip coupling capacitor leads to a coupling time constant
of 10 us. Such a long time constant is needed to limit baseline wander
with scrambled data, as independent analysis by Rick Walker, Steve
Anderson, and me indicate.
Generating such a long time constant is going to be hard in today's deep
sub-micron processes. One could use, for instance, a 100pF capacitor
and a 100 kOhm resistor, but size of both components would be a problem,
parasitics in the capacitor will make meeting return loss specs hard and
leakage current through the 100 kOhm resistor may casue offset problem.
charles
|--------------------------------------------------------------------|
| Charles Moore
| Avago Technologies
| ISD
| charles.moore@avagotech.com
| (970) 288-4561
|--------------------------------------------------------------------|
Jia Gongxian wrote:
> Hi Vicente,Steve,All,
>
> I have same concern about the AC coupling, according to the draft,
AC
> compactors does belong to RX, but doesn't clearly say, whether its in
> linecard or in IC chip, I do think these will cause problems while we
> design a system. if in linecard, the pad and vias will surely cause
the
> impedance discontinuity, different processing in AC coupling area of
> PCB will have different effect on the channel performance. How well
> we will process the AC compactors area ? As a system designer, I don't
> know, because the spec of backplane channel doesn't include this
part.
>
> In order to reduce the risk, I do agree Vicente that it's a better
> choice that place the AC coupling into the IC package.
>
> Regards,
>
> Jia Gongxian
>
> Huawei Technologies Co.,Ltd.
>
> ----- Original Message -----
> *From:* Steve Anderson <mailto:steve.anderson@XILINX.COM>
> *To:* STDS-802-3-BLADE@listserv.ieee.org
> <mailto:STDS-802-3-BLADE@listserv.ieee.org>
> *Sent:* Wednesday, May 31, 2006 11:02 PM
> *Subject:* Re: [BP] DC block capacitors in 10G NRZ channels
>
>
>
> Hi Vicente, all:
>
>
>
> I share your concern. I don't think that the draft
> standard correctly deals with
>
> the topology that you describe. I commented on this in an earlier
> draft of the standard.
>
> I think we need to say what is meant by AC coupling by providing
one
> or more
>
> specifications that place some bounds on it.
>
>
>
> Regards,
>
>
>
> Steve A.
>
>
>
>
>
>
------------------------------------------------------------------------
>
> *From:* Mellitz, Richard [mailto:richard.mellitz@intel.com]
> *Sent:* Tuesday, May 30, 2006 8:53 PM
> *To:* STDS-802-3-BLADE@listserv.ieee.org
> *Subject:* Re: [BP] DC block capacitors in 10G NRZ channels
>
>
>
> Hi Vicente,
>
>
>
> 803.3ap really doesn't say the caps are on the board. The cap is
> after TP4 and is the domain of the Rx. Yes it's a challenge for
chip
> folks as they will need to tell there customers how to deal with
> this issue.
>
> Regards,
>
> Rich Mellitz, Intel
>
>
>
>
>
>
>
> -----Original Message-----
> From: Cavanna, Vicente Vaca (Sr. ; ProCurve ASICs)
> [mailto:vicente.cavanna@HP.COM]
> Sent: Tuesday, May 30, 2006 6:45 PM
> To: STDS-802-3-BLADE@listserv.ieee.org
> Subject: [BP] DC block capacitors in 10G NRZ channels
>
>
>
> Hello colleagues,
>
>
>
> I would like to understand the perspective of the group with
regards to
>
> external DC block capacitors in 10Gbps channels such as the one
being
>
> designed by this group. My past experience indicates it will be
>
> difficult to find DC block capacitors that are specified for
operation
>
> at 5GHz and beyond - at least capacitors that are priced
reasonably such
>
> that their cost is a small proportion of the link cost. In the
farily
>
> recent past I have had difficulty finding capacitors with low
enough
>
> ESRs even at 4Gbps operation.
>
>
>
> Even if such a capacitor is found the transmission line
discontinuities
>
> (vias, pads etc) associated with such capacitors present a
significant
>
> degradation that would be nice to eliminate.
>
>
>
> I will ask a secondary question.
>
> Has it been considered to require the DC block capacitor to be
internal?
>
> Many SERDES vendors have DC blocks integrated within their
receivers and
>
> located downstream from the internal 50 ohm termination but
upstream
>
> from their receiver bias network (which has much larger impedance
than
>
> 50 ohms). Such placement allows the capacitor to be much smaller
in
>
> value and thus integrateable and still allows the receiver to be
biased
>
> independently of the transmitter which I believe is the main
purpose of
>
> the DC block. Another benefit of the internal capacitor is that it
will
>
> not have the associated discontinuties that an external capacitor
will
>
> have.
>
>
>
> Thanks in anticipation of your reply.
>
>
>
>
>
> Vicente Cavanna
>
> HP ProCurve Networking
>