Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

Re: [802.3_10SPE] Feasibility of 147.3.5 Collision detection

Hi Philip,

These are all great questions that should be obvious when reading the working group ballot drafts.  If it is not clear to you (not to me too, and have unresolved comments from D2.0, D2.2), you should submit a comment. Ballot closes this Saturday.

best regards,

Yong Kim, affiliation: NIO

On Thu, Feb 7, 2019 at 1:12 AM Philip Axer <philip.axer@xxxxxxx> wrote:

Hi All, Hi Piergiorgio,


I have a question regarding 147.3.5 (Collision detection). Earlier versions of the draft gave an implementation guideline or hint towards comparing the RX symbols with the TX symbols to detect a collision. The newer draft D2p2 states that the method is implementation dependent. Is there evidence that there is at least one known method which can reliably detect collisions in all topology scenarios? And if not, is this a problem?


The electrical characteristics of older 10Mbps 802.3 standards (I think 10BASE2 and 5) drive current into the wire, hence during collisions the DC voltage component of the signal during frame transmission can be used to detect a collision reliably.


Now with 10BASE-T1S this seems to be different. Multiple drivers will cause impedance mismatch plus a superposition of their signals. But as far as I understand the concept, apart from this there is no intrinsic mechanism to reliably detect multiple drivers. Given that the only incarnation of a collision are random bit errors on the RX wire when compared to what it transmitted on TX, what is the likelihood of not detecting those? Especially during reasonably short symbol groups such as BEACON or COMMIT. The draft says that COL shall be asserted within 256 bit times,  this would imply collisions of PLCA control commands would not be detectable. Is this intended?


In 147.3.5 b)  it is stated that a third PHY shall assert CRS in case two or more stations cause a collision. Does the CRS need to be asserted during the entire time that the drivers are driving or is the CRS allowed to glitch? What is the maximum allowed delay from reaching differential zero on the MDI until CRS is deasserted at the MII? What is the minimum required time from driving the differential pair to +-1 until CRS shall be asserted?


Assuming a worst-case attenuation through the wire, there is probably a chance that a transceiver is not even ‘seeing’ the far end driver because it overdrives its. Perhaps there is simulation data available which I am not aware of.




To unsubscribe from the STDS-802-3-10SPE list, click the following link:

To unsubscribe from the STDS-802-3-10SPE list, click the following link: