RE: [EFM] An Important FEC Issue
I think I can try to answer some of your questions which are based
on our experience.
But before we are looking for the changes for low BER you have asked,
do you know what are the numbers for high BER.
I have'nt seen those numbers in the reflector (maybe I missed them).
Also I need to know what are the assumptions:
1. What jitter specification do you assume. Is it as specified
in 802.3 (38.5) or other?
2. Do you assume a standard PLL based CDR or other CDR which
was designed for burst-mode?
3. What is the frequency difference between the ONU and the OLT?
4. What is the degradation in BER you agree to have?
(By the way, I will be happy if you can join me to the FEC email list.)
From: larry rennie [mailto:Larry.Rennie@xxxxxxx]
Sent: Wednesday, September 11, 2002 12:28 AM
To: EFM TF
Subject: [EFM] An Important FEC Issue
As you may know or not no there is a small group of us that have been
looking into FEC for EFM. The group includes myself, Lior Khermosh,
Frank Effenberger, Ajay Gummalla, Ali Abaye, Massoud Khansari, Pat
Thaler, Jonathan Thatcher, Vipul Bhatt and a few others. One of the
main issues we have run into is not the FEC itself but the effect of the
lower line BER
(1E-4) on pre FEC decoder blocks, such as the CDR. With the FEC that is
being proposed, the FEC decoder will correct a BER from 10E-4 to 10E-12.
In case you have forgotten, this is an optical coding gain of about 3dB
(more PON splits) and, equally or perhaps more important, improves reach
of a MPN limited link by 50% for links with MPN penalty of about 2dB.
Details on the improvement from FEC and its benefits are covered in
presentations already made before the group. Back to the issue at hand.
Clearly the CDR operation will degrade (slower lock time, etc) when it
is asked to operate with a line BER of 10E-4, but by how much? So far
we have not had much feedback on this issue from within our little
group. This is not surprising since we are not PMA or CDR experts. For
this reason we have decided to post this specific issue to the larger
EFM reflector in the hope of getting some feedback. Does anyone have any
thoughts on this issue? Some of the performance changes to consider
1. Changes in CDR lock time of the PMA under high BER conditions. 2.
Changes in the ability to maintain CDR lock under high BER conditions.
3. Changes in the jitter characteristics under high BER conditions
(primarily TP4) 4. Changes in the synchronization lock time in the PCS
under high BER conditions. 5. Changes in ability to maintain
synchronization lock in high BER conditions
One way to learn about this issue is to do some lab experiments with
existing transceivers. But before we do that, perhaps some of the
answers already exist.