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For those who were absent in Seoul meeting I'll recap the frame format issue here.
There were two comments trying to change the MPCP frame format. (in REGISTER, and in GATE message)
- comment #858 proposed to put a padding byte or extend the one-byte field to two byte to make the fields 16-bit aligned in GATE message.(The gate is the most frequent message, and for people who might try to generate gate frame using external CPU, it'll help. Of course the start time should be set by hardware. Other messages are 16 bit aligned)
- comment #288 proposed to change the order of fields in REGISTER message so that the flag is placed right behind the time stamp like other messages. (currently, "assigned port" comes before flag, while in all other messages, flag or flag-like things comes always first)
In EPON STF, The motion to adopt this comments(a slightly revised motion) passed and the motion was brought up in EFM closing plenary because it was deemed important and demands attention of all EFM members. It failed by a close margin but we could see there are many in favor of this change.
Some people don't want to change it because they have ASIC already implemented or being fabricated. For others doing it with FPGA, or not implementing it, changing the format only seems right.(Changing the format will be a trouble for some people.)
I would like to hear what others are thinking about this issue. I'm not insisting we should change the format. I know that there is no big deal in the format. With the current spec, if the gate frame is generated by the external CPU(which seems to be the only practial reason for changing), the hardware can still adjust the format before transmission maintaining the external CPU interface 16 bit alligned. It's just to make it look nice. Neverthless, it seems still good to change the format and I want to see if some of the people have changed their minds during the past period. If there is still strong opposition, I'll not raise this issue because I don't want to be hated by some folks. : )