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After the Ottawa meeting, Chris DiMinico and I discussed 100GE Cu, and had a few observations to share on the HSSG reflector.
The approaches to 100 GbE Cu presented to the HSSG to date are 10 x 10Gb/s, 4x 20Gb/s and 4 x 25Gb/s using balanced differential pairs consisting of one differential path for each direction; the 10x10Gb/s utilizes 20 differential pairs and both 4x20 Gb/s and 4x25 Gb/s utilizes eight pairs. In terms of technical challenges, a 10 Gb/s link can already be implemented for at least 10 meters with today’s technology, as shown in the DiMinico HSSG presentation last week.
25 Gb/s signaling was demonstrated as technically feasible over copper and offers the lowest differential pair count, but is much more technically challenging. Considerations for transceiver complexity versus PMD/MDI attributes i.e., number of copper lanes, board area, connector footprint, and the size and cost of the copper cable assembly will be key factors in determining the optimal number of lanes and rates.
Standardizing backplane interfaces
In the future, SMF Modules will benefit from availability of 25 Gb/s I/O capable CMOS, by enabling the reduction in I/O lane count (and the removal of SerDes functionality required by some first generation proposed architectures.) Cu Modules will also similarly benefit by using a 4 x 25Gb/s interface to the system. It will very beneficial to coordinate interface requirements, and work with the OIF CEI-25 effort to maximize applicability to a variety of applications.
Perhaps Joel Goergen could give an overview on the HSSG reflector on the CEI-25 effort, including projected timelines and applications.