Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

Re: [HSSG] Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R), query

There are two reasons.
One is in the name "sync header." One always has a transition between the two bits of the sync header. The rest of the 66 bit block is scrambled so at any other position between two bits of the 66 bit block one has a 50% chance of having a transition. This is used to obtain block sync.
The other reason is error detection robustness. If there was a single bit difference between a data block and a control block, one could create a false end of packet or start of packet with two bit errors. For example, one might have two data blocks in sequence in a packet where the block payload was the same as the block payload in a valid end of packet followed by idle. If bit errors in the sync header turned both those into control blocks, then a false end of packet could be created with two bit errors and if the last 4 bytes of the false packet happened to match the CRC we would deliver a false packet. With a 2 bit sync header, it takes a minimum of 4 bit errors to create a false start or end of packet giving us a 4-bit Hamming distance.

From: Hari S. patel []
Sent: Monday, September 17, 2007 6:28 AM
Subject: [HSSG] Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R), query

I have a question on Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R).

We have two bits for sync header having following meaning,

00 - Invalid block
01 - Data block 
10 - Control block
11 - Invalid block

I get confused,why we have taken two bits, even if we can indicate data/control block using one bit only.
Can I know the reason,why is it so?

Hari S. Patel