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I have interest to understand this as well. I feel the laser driver doesnot have to be CMOS such as in 10G for better performance.
I think what in Matt’s slides actually talking about the high-speed driver portion of the CDR, which indicated in its Ref.1 of pg.11 by Toifl. Here is what I can find from google search for this Ref.
12.3 A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS
T. Toifl, C. Menolfi, P. Buchmann, C. Hagleitner, M. Kossel, T. Morf, J. Weiss,
A quarter-rate CDR circuit is based on a dual-loop approach where sampling phases are
generated by a phase-programmable PLL that is controlled by a digital DLL.
Implemented in 65nm SOI CMOS, the chip occupies 0.03mm2 and consumes
1.8mW/Gb/s. Measurements confirm 40Gb/s operation with a BER <10-12 at a maximum
frequency-offset of 400ppm. The phase relation between data and edge samples can be
programmed within ±0.1UI.
From: Ali Ghiasi [mailto:aghiasi@xxxxxxxxxxxx]
The reference for page 11 is the same as the reference on page 8 -- Yagisawa-san's paper. My apologies that this was not clearer in the presentation.
On Wed, Sep 3, 2008 at 3:14 PM, Ali Ghiasi <aghiasi@xxxxxxxxxxxx> wrote: