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Re: [802.3BA] FEC Block synchronization

   This is an implementation choice.

   The specification just describes functionality (not implementations).
The specification does not place any constraint on synchronization time.
It is up to the implementor to decide what trade-offs to make in
designing their synchronizer.


-----Original Message-----
From: Tarun Aggarwal [mailto:tarun_agarwal@xxxxxxxxxx] 
Sent: 26 May 2009 14:57
To: STDS-802-3-HSSG@xxxxxxxxxxxxxxxxx
Subject: [802.3BA] FEC Block synchronization


The text in of draft D2.0 for 802.3ba says:

"2) Evaluate parity for the potential block
i) If the parity does not match (i.e., the received parity does not 
match the computed parity),
shift candidate start by one bit position and try again."

Let us say first 2112 bits are received with a bad CRC. Now when 2113rd 
bit comes,
Does the text suggest to recalculate CRC at this moment itself (taking 
2113rd bit and previous 2111 bits) and similarly keep doing this at 
every bit received
(requiring a buffer of 2112 bits)


Does it suggest that 2113rd bit be ignored and receiver should wait for 
next set of 2112 bits to arrive before recalculating CRC?

In first case, descrambling and CRC calculation needs to be done for 
every bit received (seems like lot of work for hardware)
but at the same time it would achieve synchronization much earlier than 
in second approach above.

Could someone please clarify in this.