Re: response to Bob Leonowich's presentation, page 17, Sept 2000
Here are some response comments:
3.) Logic side power plane residence of detection implies EMI can leak from
noisy logic to wire
The exact same thing is true of the 10/100/1000 data paths.
EMI problems will be dominated by the switching power supply
rhl: It seems the common-mode EMI blocking of the data path's transformers
should be different than that from the signature transformer's?
4.) Approximately 1MHz bandwidth signature pulse signaling precludes aggressive
limit noise emissions
If you look at page 27 of my presentation, the common mode discovery pulse
energy is about 40 dB down
at 1 MHz, the 3 dB point is more like 30 KHz.
rhl: To clarify, I meant without a bandwidth constraint in series with the power
supply, the user is
free to filter at any corner frequency to eliminate noise from the supply
when/if that becomes an issue
down the road. If the AC pathway must be kept clear, that is one more obstacle
suppressing power supply noise.
5.) Conveyance of current use from supply to upper levels (to facilitate network
management) requires crossing the isolation barrier and additional monitoring
This is not tied to the discovery method.
rhl: However, there seems to be an additional cost associated with providing
in the diode scheme (as presented) since the increased cost of the power module
with and without this function was not given.
7.) Parallel devices may get destroyed at application of higher power
Can you be more specific about which parallel devices you are talking about?
rhl: This attempts to address the devices outlined in Bob Bell's liaison input
to us from:
TIA TR41.4 Subcommittee on VoIP Gateways and Infrastructures
"The ISDN system might legitimately have multiple S-Bus devices on
the same 4-pair cable which terminates using "RJ45"-type connectors. If
that cable is reused for an 802.3 network, the endpoint might very well
respond to the detection scheme within the detection parameters but when
power is applied, parallel connected surge protectors left over from the
ISDN usage might overheat and cause a fire if subjected to the nominal
voltage and if the current is not limited correctly."
It also can pertain to test equipment that does not appreciably conduct at
low voltage (<2V) but does at higher voltage (>6V). A higher signature voltage
allows these devices to be detected before having 15W of power applied.
11.) 1uF >54V signature cap in PE is big and expensive
The cost needs to be considered. Also, the cap value can probably be lowered.
Even so a 1206 part is not that big.
rhl: The DTE would appear to need 2 of these cap/signature modules for
power on signal/spare pair with the diode scheme.
This is not true on the resistive scheme.
> Rick Brooks wrote:
> I'm sorry that I was not at the meeting to answer these questions.
> Here are my responses to the item numbers on your presentation, page 17
> 1.) Transformer doesn't necessarily provide AC/ESD impulse isolation so this
> needs to be
> ESD was tested informally, but not reported.
> Recall that the logic side of the transformer has a 100 ohm and a 3300 pf cap
> to ground.
> This shunts the ESD energy that gets through the transformer.
> This is much easier than on the data lines, since the pulse bandwidth is so
> much lower.
> 2.) Strategy implies PHY redesign and consequential re-qualification on new
> devices with higher pincount to support the needed I/O
> My method can be implemented in the PHY, or in the power supply, whichever is
> more cost effective.
> My prototype shows a PHY configuration.
> 3.) Logic side power plane residence of detection implies EMI can leak from
> noisy logic to wire
> The exact same thing is true of the 10/100/1000 data paths.
> EMI problems will be dominated by the switching power supply
> 4.) Approximately 1MHz bandwidth signature pulse signaling precludes
> aggressive filtering to
> limit noise emissions
> If you look at page 27 of my presentation, the common mode discovery pulse
> energy is about 40 dB down
> at 1 MHz, the 3 dB point is more like 30 KHz.
> 5.) Conveyance of current use from supply to upper levels (to facilitate
> network power
> management) requires crossing the isolation barrier and additional monitoring
> circuits in
> the supply
> This is not tied to the discovery method.
> 6.) Longitudinal voltage characterization in terms of <1 volt sensitivity has
> not been done
> What exact tests are you asking for?
> 7.) Parallel devices may get destroyed at application of higher power
> Can you be more specific about which parallel devices you are talking about?
> 8.) Use of constant signaling and reliance on transformer saturation to detect
> undercurrent is
> very coarse. >10mA signature pulses imply a >0.5W maintenance consumption
> The prototype we built uses the power supply to detect a minimum load. It
> could use transformer saturation, if
> that is practical, I'm hearing that the magnetics vendors are against it.
> Again, this is a separate issue from the discovery method.
> Also, what does the amplitude of the signature pulse have to do with power?
> When the DTE power is on, and the undercurrent value matters, and the
> discovery pulses are off.
> 9.) 25 pair bundle interference with asynchronous units?
> This is on my list of things to test.
> 10.) Pulse shaping implies expensive immediate implementation
> This is true if you use my discrete approach, but why would anybody do that?
> An integrated IC solution would use multiple current sources, as the PHY's do
> 11.) 1uF >54V signature cap in PE is big and expensive
> The cost needs to be considered. Also, the cap value can probably be lowered.
> Even so a 1206 part is not that big.
> 12.) Extra two diode drops Required in PE lowers maximum power delivered to PE
> We could use a FET switch instead. All discovery methods, except the large
> cap, face this problem of removing
> the effect of the 100 to 500 uF cap on the input of the power supply on
> any comments?
> - Rick