RE: Candidate Detection Tolerance Allocation and Test Limits
I confess that I have been merely monitoring the progress of the group, as
compared to actually keeping up with the technical developments. So, I have
only a fuzzy sense of what the slope calculation is all about. Nonetheless,
I wanted to put in my two cents on the subject of precision.
In IC design, you are lucky to get 15% absolute control on anything over
process and temperature. Through the use of an off-chip resistor, it is
easily possible to generate a reference current which is proportional to the
off-chip resistor and an on-chip reference voltage to within 2% or so.
However, the reference voltage itself will only be controlled to around 5%.
So, the current can be off by something like 7%, worst case. In principle,
it should be possible to use the reference current and the reference voltage
to establish the slope of a V/I characteristic in such a way that the
voltage reference drops out and the measurement is ratiometric with respect
to the off-chip resistor. However, even then it would be easy to accumulate
errors on the order of 3-4%. So, given a choice between requiring 3%, 5% or
8% precision from the PSE slope detector, only 8% makes the design trivial.
5% will require great care. 3% may require elaborate self-calibration. All
of this assumes that trimming is disallowed for cost reasons.
The bottom line is that while it is possible on an IC to replicate zillions
of elements with good matching (<1% with care), absolute control is tough.
You can't just pull a 1% resistor or 2% voltage reference out of your kit
bag and go from there, and each signal manipulation is likely to cost you 1%
in your error budget. So, give the PSE detection circuit as much slop as
Again, my apologies if I have totally misunderstood the question, but the
general guidance remains valid.
Cicada Semiconductor, Inc.
[mailto:owner-stds-802-3-pwrviamdi@xxxxxxxx] On Behalf Of Donald S. Stewart
Sent: Tuesday, November 21, 2000 8:17 AM
Cc: Donald Stewart
Subject: Candidate Detection Tolerance Allocation and Test Limits
At my request, David Law has posted slides that attempt to tune up the
tolerance allocation limits presented at the Nov IEEE meeting. Please see,
Those slides give three scenarios. The only difference is the slope
calculation precision assumed for the PSE (+/- 3%, +/- 5%, +/- 8%).
The intent is to help move us to agreement on a slope determination
precision level that is practical for analog devices (no micro controller),
while still accepting a fairly
compact part of V-I space.
**** I particularly invite input from silicon house representatives (as
well as others), on the feasibility/acceptability of these three cases. I
would lean toward keeping to +/- 5% or lower, but we need discussion.
The basic allocation philosophy is to keep tolerance tight on the PD and to
allow the PSE to
accept a wider area to ensure power delivery. Keeping PD tolerance tight
also facilitates having less precision in PSE slope determination, and
space for multiple power classes IF that is adopted.
I think it would be good to keep the final budget in an appendix of the
standard to show how we got to where we did.
The accept/reject template concept is consistent with what we discussed in
Tampa and similar to Rick Brooks' recent templates. These slides
concentrate on "what numbers" and why.
Donald (Don) S. Stewart Phone: 732-817-5495, FAX x4666
Avaya Inc. e-mail: dsstewart@xxxxxxxxx
101 Crawfords Corner Road
Holmdel, NJ 07733