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RE: tolerance analysis of resistive method

After looking over Rick Brooks' files in some detail, I think we all need to
be prepared in Irvine to review the exact signature mechanism which makes
the most sense.  The tolerance budget permitted by the use of 25k/75k is
very tight, if we use Avaya's assumptions regarding leakage current

I additionally have modified Rick's MathCad files to look at a 10k/30k
resistor combination, in the hopes that using a lower overall resistance
would have a significant effect upon the tolerance budget by swamping some
of the leakage currents which make this error budget so tight.  Even at
10k/30k, there is little improvement using Avaya's assumed leakage currents.

Of equal or greater concern to me is that I am not sure that this leakage
current budget can realistically be guaranteed with even the best
reasonably-priced MOSFETs and rectifier diodes which I can locate on the Web
from any major manufacturer (e.g., ST Micro's STRIPFets and 1N4934 rectifier

I believe that we would be better served by using a signature device which
can reasonably accommodate between 1mA and 3mA of current during the probe
interval, and then have no excessive dissipation while the PD is operating.
One way of accomplishing this is to specify a constant-current sink of 2mA
+/- 20%.  In that case, the probe currents will be raised by a factor of 20,
which will swamp stray leakage currents, and yet the total current sink
dissipation at -57V would never exceed (57V x 2.2mA) = 0.1368W ~ 1/8W.
While the first generation of such current sinks might have to be
constructed from discrete components, these components could be incorporated
into the PD's DC-DC converter to reduce board space and take advantage of
volume production.  I believe it would not be long before the semiconductor
industry would then bring out a three-terminal device which would be
specifically intended as a 2mA signature-element current sink (with a
disable pin if desired).

As ever, comments are appreciated.

Peter Schwartz 
Applications Engineer
Micrel Semiconductor
Phone:	408.435.2460
FAX:	408.456.0490


Happy New Year to all 
is this the first reflector email of the new millennium? 

I just wanted to make everyone aware of a tolerance analysis that I did 
regarding the two point resistive method of discovery. 

There are two Thevenin voltage sources, V1 and V2 (the two probing
Ideally V1=24V and V2=12V, so V2 = 0.5 * V1. 

The analysis looks at the worst case tolerances of: 
the 75K source resistor res_tol, 
the tolerance of the 1st source V1, src_tol, 
and the tolerance of the 2nd source voltage V2 relative to the 1st source
voltage, this is called src_rel_tol. 

I start with the desired valid signature range of 19K to 26.5K. 
Then I derive what the window detector voltages must be in order to
guarantee that a valid signature will 
always be correctly recognized. 
Then, given those defined window detector voltages, I again use worst case
tolerances to determine 
what range of signature resistance will be guaranteed to be rejected. 
At present, it looks like tolerances of around 1% will be needed, or we will
need some 
form of calibration, or maybe we will need to change signature values, 

Check the analysis file out at:

see you in Irvine, 
- Rick