RE: PSE vs. PD power dissipation again
See my comments bellow.
> -----Original Message-----
> From: Lynch, Brian [SMTP:brian_lynch@xxxxxx]
> Sent: ד, מרץ 21, 2001 5:12 PM
> To: 'Yair Darshan'; 'Dave Dwelley'; stds-802-3-pwrviamdi@xxxxxxxx
> Subject: RE: PSE vs. PD power dissipation again
> Yair, Dave, all,
> I'll throw some more fuel to the fire below...
> >-----Original Message-----
> >From: Yair Darshan [mailto:YairD@xxxxxxxxxxxxxx]
> >Sent: Wednesday, March 21, 2001 5:06 AM
> >To: 'Dave Dwelley'; stds-802-3-pwrviamdi@xxxxxxxx
> >Subject: RE: PSE vs. PD power dissipation again
> >See my comments bellow.
> >> -----Original Message-----
> >> From: Dave Dwelley [SMTP:ddwelley@xxxxxxxxxx]
> >> Sent: ? ??? 21 2001 4:43
> >> To: stds-802-3-pwrviamdi@xxxxxxxx
> >> Subject: PSE vs. PD power dissipation again
> >> Group -
> >> In lieu of a dedicated power ad-hoc reflector, I'm posting
> >this to the
> >> general list. Is there a power reflector in the works?
> >> I'm assuming that we'd eventually like to integrate the
> >power switches
> >> into
> >> a PSE chip, and that PSE designers will tend to want to
> >service multiple
> >> channels with a single chip: 4, 8, or more.
> > [Yair Darshan] (1) Yes we would like it, if it will
> >not increase
> >system cost and complexity (PSE and PD).
> >> Also, I assume that we'd like
> >> to be able to power up many PDs simultaneously (when the
> >wiring closet
> >> power comes back on after a California shutdown) - this
> >isn't critical,
> >> but
> >> it's desirable.
> > [Yair Darshan] (2) I don't think it is an issue at
> >all, since after
> >break down of long time, it is not important if a PD will get service
> > right now or within few seconds.
> [Brian Lynch] If it is OK for a PD to get service "within a few seconds"
> why do we concentrate so much on detection/classification time? If, by
> a classification step to discovery, we add 200ms, is that a problem? How
> much time
> will it take for the 100th port to come alive in a large system?
[Yair Darshan] I guess we have two scenarios: Case 1: Normal
operation, a new PD is hooked up to the system. What is the normal time that
the technician expect to get service with out thinking that some thing is
wrong? My opinion is 3-6 second. If the system has 100 ports or more and it
has some impact on detection time, with specific implementation and in other
implementation it is not an issue. Example: If the detection is done port by
port sequentially, than detection time is one of the major factor that sets
the "service time" . If the detection is done simultaneously for all the
port, than it has a little effect on service time.
In my opinion, the detection time is what it is since the detection
concept that finally we have chosen dictates the suggested 500mSec (with
due to the fact that it is a function of high impedance and some
Case 2: If we had problems for few hours or so, what is few seconds
I do not think that adding 200mSec for classification step is a real
problem. I personally, like the idea.
> >> To do this, we need a scheme that keeps the power
> >dissipation out of the
> >> PSE end.
> > [Yair Darshan] Agree. Remember that we have two cases of power
> >dissipation. Case 1: during startup. Case 2: During normal operation.
> > In Case 1: We indeed can reduce the power loss in PSE switch by
> >setting the PD current limit lower than the PSE, we are not "kill" the
> >problem completely, we just moving it to the PD with some ability of
> >reducing it by increasing PD cost.
> [Brian Lynch] I agree that in startup the power has to be lost in either
> the PSE or the PD. That is physics. By putting the inrush current limit
> on the PD side, and setting the current limit to a value below the current
> limit in the PSE, we get a number of advantages.
> - The PSE switch losses are always low. Turn ON losses
> can be limited to 300mw for the initial "spike" and continuous
> operation losses are in the 100mw region. (assuming a 1 ohm MOSFET).
> In a practical case, the RdsON will be much less. A SOT-223 FET or SO-8
[Yair Darshan] NOW TAKE THE ABOVE ADVANTAGES THAT YOU SUGGESTED AND
SET THE PSE INRUSH CURRENT LIMIT TO BE HIGHER THAN THE PD(ACTUALLY THE PD
WILL NOT HAVE INRUSH CURRENT LIMIT FUNCTION) AND YOU WILL GET THE SAME
ADVANTAGES IN PD........
(THE ISOLATING SWITCH CAN BE A VERY SMALL FET NOW, SINCE IT CAN BE
DESIGN AS A SWITCH)
> RdsON in the .02 to .05 range will dissipate much less.
[Yair Darshan] Correct, However SO8 Mosfet with low RDSON is much
expensive than 0.5Ohm-1Ohm Mosfet. If you use the Mosfet as external
component and not integrated in a chip, you can dramatically reduce the cost
of the Mosfet.
> - In a fault condition (as a shorted wire) the reaction time may be
> virtually instantaneous, keeping PSE switch losses low.
[Yair Darshan] Correct, you can set the Inrush current limiter to
turn off fast in case of short in both concepts..
> - The PD designer has the freedom to choose the size and rate of
> charge of
> his PD's bulk capacitor, and thus the size of the MOSFET used.
[Yair Darshan] Correct, but don't you agree that it is better that
he will not need to use this component at all in the PD?
> A low cost PD
> can use a small MOSFET, and a higher end device may use a larger.
[Yair Darshan] Correct, but all the functions you have mentioned
are already exist on the PSE (sense resistor, mosfet, opams etc) and now we
are arguing on the mosfet package size which is not important since the
overall cost is much larger if we add additional function to the PD. AND we
don't save cost in PSE...
> The point
> is that
> PD can be sized to the job, and not be limited by avoidable constraints.
[Yair Darshan] Correct, however why to put additional function and
size it to the job if we can eliminate it thus we don't need to size
> If the PSE limits the inrush current:
> - The PSE muse always be sized for the worst case, which is at least
[Yair Darshan] Correct, See above why it is not aproblem.
> 350ma for the maximum startup time allowed. So for large systems and
> the PSE
> would need to have and expensive D2PAK MOSFET on every port.
[Yair Darshan] I don't agree with you in this point. Popular part
numbers of suitable D2PACK are lower in cost compared to low RDSON SOT223 OR
> - Under a shorted wire condition, the switch must stay on for and
> period of time.
[Yair Darshan] Correct, however, if we agree to the whole concept
advantages mentioned above, it is not aproblem.
> (A time greater than the longest startup time). If the
> current limit is
> set at 500ma, then the losses could be as high as 57*.5=28.5 wats for up
[Yair Darshan] Why 500mSec? 100mSec or even 50mSec is enough.
> - The size of the PD bulk capacitor must be limited, and the time to
> must be limited in the spec, constraining future design freedom.
[Yair Darshan] We don't need design freedom where it is not
required. 15W switching mode power supply working at the popular 100KHZ,
does not need
more than 470uF in its input. Guaranteed.
> - To avoid startup issues, additional circuitry is needed in the PD
> to keep
> the switch ON while the PSE voltage drops to zero and begins charging the
> bulk capacitor.
[Yair Darshan] If you are referring to the isolating switch, you
don't need additional circuit. it works fine as presented.
The PD power supply will need the UVLO
function in any concept after the big cap, and you can have it free in
The PD power supply will not need UVLO
function when linear regulator or un regulated power supply is used.
> The added circuitry must have energy storage in it sufficient to keep the
> switch alive for the
> time it takes to charge the capacitor....more cost and potential for
> to start up.
[Yair Darshan] I think you miss the point here, or you are in favor
of putting the inrush current limiter in the PSE....., you can have delay
function by adding a cap if you want, but it is not a must since we can
allow the drop in the spec. In the circuit presented in March, there is no
drop, the voltage is going down to around 20-30V.
We will have drop only if the isolating switch will work as a fast
> > Case 2: During normal operation we need to support
> >350mA avg, with
> >57V output. It means a 80-100V, 0.6-1A MOSFET which its die
> >size is function
> >of the Rdson. At 350mA average current the power loss on the
> >FET will be
> [Brian Lynch] 100mw/port or less.
> > In low cost plastic package you can dissipate between
> >1-1.5W thus to
> >meet this number you will need low Rdson MOSFET
> > which will have large die size.
> > We didn't mention yet what we will need with current
> >peaks above the
> >average which is normal situation at some loads.
> [Brian Lynch] The peak current requirements, no matter what they are, will
> only the change the numbers, not their relative positioning.
[Yair Darshan] Correct.
> > To summarize this: I am not sure that integrating the
> >Mosfets in the
> >chip will get us important advantages.
> > Info received from chip vendors shows that:
> > a- They have the technology to implement MOSFET (HV technology )
> >with the chip (Low voltage technology)
> > b- Integrating the MOSFET into the chip will not save footprint
> >since the die size is large which will increase the package size.
> > c- The cost of integrated chip+Mosfet is greater than
> >the cost of
> >low power low voltage small package chip with external MOSFET.
> > In light of the above what is the incentive to
> >integrate the Mosfets
> >into the chip?
> >> Rick and Dieter have both shown that if the PD limits inrush
> >> current to some value lower than the PSE current limit (eg.,
> >350mA for the
> >> PD, 500mA for the PSE), dissipation in the PSE is near zero.
> > [Yair Darshan] Dissipation on PSE switch is very low and
> >dissipation on PD switch is very high.
> [Brian Lynch] The loss in the PD switch FET can be limited to any value,
> depending on the startup time allowed. It can be as high as 10watts for
> startup (into a 100uf capacitor charging to 57 volts) or as low as 200mw
> longer period of time, then less than 100mw continuous. It is up to the PD
> designer to
> decide the trade offs he is willing to make.
> >> This one of
> >> several options allowed by the draft standard as it reads
> >now - others
> >> share the dissipation between the two ends (the Avaya
> >resistor divider/FET
> >> scheme), or put all the dissipation in the PSE (the
> >UVLO/latch-on scheme
> >> that Micrel showed at the meeting).
> >> If we allow any PD to push any dissipation back into the
> >PSE, we force the
> >> PSE to be able to handle the worst case - all channels powering
> >> simultaneously, with all the power in the PSE.
> > [Yair Darshan] All channels are not required to startup
> >simultaneously. After detection we can turn on each channel
> > at atime since we have control on it according to management
> [Brian Lynch] Will mid-span have the same intelligence for startup?
[Yair Darshan] Yes, it does not matter if it is a mid span or final
switch solution since the Powering process and the detection process and
management requirements, needs some inteligence.Thus adding few more lines
in the software is free.
> >> To do this, the PSE needs
> >> some accommodation: heat sinks,
> > [Yair Darshan] No heat sink required. With D2PACK, we
> >can support
> >easily 500mA peak for 100mSec.
> > Now, if we reduce the time from
> >100mSec to
> >40-50mS it is even better.
> [Brian Lynch] Perhaps better for dissipation in the PSE switch, but worse
> for a PD designer, since now EVERY PD must start in a certain time. Low
> high end.
[Yair Darshan] What is the problem if all PD's will startup at a
time limited by the current and time specified in the PSE. I can say for
sure that PD designers will be happy to get this service from PSE since it
saves them allot of components and inter-operate problems.
I don't see aproblem from PD side, since I believe that the PD is
more sensitive to cost and we should relax it as much as we can and use the
functions and intelligence that we have already in PSE and we need them
anyway from other requirements of the spec.
> >> external FETs,
> > [Yair Darshan] Agreed.
> >> sequential power up algorithms (which lengthen average
> >detect time), o
> >> low current limits at startup. None of these are desirable.
> > [Yair Darshan] - Sequential power up algorithm is
> >easy to get with
> >no cost. We will need some intelligence in any case.
> > this requirement is part of it. It will help reducing
> >power supply
> >size and many other good advantages.
> > [Yair Darshan] - It will not affect detection time,
> >it will affect
> >the time that the PD is turning on, However we agreed that it is not an
> >issue, since boot up time can be long ( Laptop, PC etc...)
> >> There is the issue of line capacitance, which will put the
> >PSE into its
> >> 500mA limit briefly (<74us) - but this short time duration won't
> >> significantly heat the PSE. We could also see a short on the
> >wire - in
> >> this
> >> case, the PSE could shut off quickly (<1ms) or incorporate
> >foldback to
> >> limit dissipation, like Micrel showed.
> > [Yair Darshan] As stated before, if we can support
> >500mS for TBD
> >ms, the above is not an issue.
> >> I propose that we mandate that the PD limit the inrush
> >current, say to
> >> 350mA +/-50mA, and mandate that the PSE limit at say 500mA
> >+/-50mA. By
> >> forcing the PD to do this, we allow a multi-channel PSE chip
> >with FETs on
> >> board. Otherwise we can't do it.
> > [Yair Darshan] I do not agree to this conclusion from
> >the reasons
> >mentioned above, and from the reasons described
> > in my presentation regarding "Where to
> >locate the inrush current limit".
> > If you do not agree to my
> >conclusions and
> >data presented there, lets discuss it and crack it,
> > until we will have the best
> >understanding of
> >what is the optimum solution for us.
> [Brian Lynch] I the 350+/-50ma and 500ma +/-50ma are reasonable numbers.
> I think putting the inrush control in the PD side provides a more robust
> solution that allows more design freedom and less opportunity for
[Yair Darshan] I don't see how you reduce opportunity for
miss-behavior, can you give some examples?
> It is relatively easy to specify, and allows designers to size their PDs
> to their own needs, without impacting system behavior.
> Yair, I think the approach you describe can be made to work in a limited
> but with so many vendors, so many designers, and so many unknown future
> I think it is prone to difficulty, not only in specifying, but in
> > In my opinion, setting the PSE to 500mA for TBD msec. and not
> >forcing inrush current limiter in the PD is the desirable solution
> > in terms of performance/cost ratio.
> > It does not mean that the PD will not have current
> >protection. It is
> >part of the PD power supply after the big cap.
> > We are discussing only on the inrush current limiter
> >that should be
> >located before the PD big cap.
> >> This does make a bare-bones PD more complicated. In the
> >short run, it
> >> probably requires a low-cost op amp and a sense resistor to
> >implement - or
> >> a 150 ohm/~1W series resistor and a FET to short it out when
> >the switcher
> >> input cap voltage approaches the line voltage
> > [Yair Darshan] All the above functions and more you
> >have already in
> >the PSE. Why duplicate it also in PD?
> [Brian Lynch] THere has to be some control for the switch in the PD.
> it is
> ON/OFF or a current limit circuit, there has to be something. A resistor
> an NPN
> would do it, too.
[Yair Darshan] Why it has to be? Are you referring to the isolating
switch? I am not sure that I understand you.
> >> Going forward, the PD
> >> function (with power device, current limit, UVLO, the works) can be
> >> integrated - and since PDs generally don't need multiple
> >channels, the
> >> power in the single switch is tolerable (as Dieter showed at
> >the meeting).
> > [Yair Darshan] The power in the switch is tolerable
> >also if it is
> >on PSE when external FET is used.
> >> The "30 watt" PD would conceivably need a dual - we'll use a bigger
> >> package
> >> or some other trick to deal with the heat in that case.
> >> How much is it worth to integrate a multi-channel PSE chip?
> > [Yair Darshan] From the data that I have today: It is
> >not worth the
> >effort. To many problems compared to trivial solution.
> > [Yair Darshan] To summarize the above, I think that we need to
> >answer the following questions:
> > 1. Do we have a space problem that integration the MOSFET in the
> >chip can help us?
> > 2. Do we have power loss problem when the fet is not integrated?
> > 3. Do we have power loss problem when the fet is integrated?
> > 4. How chip cost affected by integrating the Mosfet
> >compared to chip
> >+ discrete Mosfet?
> > 5. Cost of multi channel chip with integrated Mosfets
> >compared to
> >multi channel chip with external Mosfets
> > 6. Foot print of multi channel chip with integrated Mosfets
> >compared to multi channel chip with external Mosfets
> > 7. Can we support many applications with low cost
> >solution when the
> >PD contains the inrush current limit function?
> > 7.1. What it does to PD cost
> > 7.2. What it does to System cost
> > 7.3. How it complicate PD design
> > 7.4. How it affect PSE-PD inter-operate
> > Yair Darshan/ PowerDsine
> >> Dave Dwelley
> >> Linear Technology