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RE: PSE vs. PD power dissipation again


See below for my reply. To help out readability, I'll edit some of
the old text. (Sorry Bruce, The internet is not always friendly to
text formatting (such as color) and so it doesn't always work. Maybe 
some separating ********* between topics will help readability).

>> [Brian Lynch] If it is OK for a PD to get service "within a few seconds"
>> then why do we concentrate so much on detection/classification time? If,
>> adding  a classification step to discovery, we add 200ms, is that a 
>> problem? How much time will it take for the 100th port to come alive in a
>> large system?

>	[Yair Darshan]  I guess we have two scenarios: Case 1: Normal
>operation, a new PD is hooked up to the system. What is the normal time
>the technician expect to get service with out thinking that some thing is
>wrong? My opinion is 3-6 second. If the system has 100 ports or more and it
>has some impact on detection time, with specific implementation and in
>implementation it is not an issue. Example: If the detection is done port
>port sequentially, than detection time is one of the major factor that sets
>the "service time" . If the detection is done simultaneously for all the
>port, than it has a little effect on service time.
>	In my opinion, the detection time is what it is since the detection
>concept that finally we have chosen dictates the suggested 500mSec (with
>good margin)due to the fact that it is a function of high impedance and
>	Case 2: If we had problems for few hours or so, what is few seconds
>	I do not think that adding 200mSec for classification 
>step is a real
>problem. I personally, like the idea.
[Brian Lynch] I agree. 
>> [Brian Lynch] I agree that in startup the power has to be lost in either 
>> the PSE or the PD. That is physics. By putting the inrush current limit 
>> on the PD side, and setting the current limit to a value below the
>> limit in the PSE, we get a number of advantages.
>> 	- The PSE switch losses are always low. Turn ON losses 
>> can be limited to 300mw for the initial "spike" and continuous  
>> operation losses are in the 100mw region. (assuming a 1 ohm MOSFET). 
>> In a practical case, the RdsON will be much less. A SOT-223 FET or SO-8
>> with
[Brian Lynch] I think we are in agreement on this point. Either the 
PSE or the PD needs to handle the inrush current, and therefore the 
burden of size and cost. Where I think we disagree is on the degree 
of limiting, and whether it is entirely in the PSE, the PD, or split 
between the two.
Perhaps If I explain my interpretation of your proposal, that will help.
1) Place the majority of the inrush control in the PSE
2) To prevent the input line from being "shorted" the instant the
bulk capacitor is connected (when vin reached 40-44 volts), place 
some amount of inrush limiting in the PD.
3) Now the power loss is split between the FETs in the PD and PSE. 
4) Limit the PD bulk capacitance to 470uF to limit the startup time to 53ms.

My comments to each of the above.
a) (2) requires that "something" needs to keep the PD switch ON. To me, 
this is at least an added cap, a diode and resistor for a TDB time interval.
b) (3) tells me that now both the PSE and PD switches need to be D2PAK.
No future integration will be possible at these power levels.
c) (2) the "some amount" of current limiting has to be well defined to 
avoid start up timing issues.
d) In the event of a shorted wire, the PSE switch must handle the short for
more than the time in (4). 26.5 watts for up to 100ms. Any faster, and
the system may not start up.
>	[Yair Darshan]  Correct, but don't you agree that it is 
>better that he will not need to use this component at all in the PD?
[Brian Lynch] I am confused here. I see one switch in the PSE and one 
in the PD.
>>  A low cost PD can use a small MOSFET, and a higher end device may use a
>	[Yair Darshan]  Correct, but all the functions you have 
>mentioned are already exist on the PSE (sense resistor, MOSFET, opams 
>etc) and now we are arguing on the MOSFET package size which is not 
>important since the overall cost is much larger if we add additional 
>function to the PD. AND we don't save cost in PSE... 

[Brian Lynch] I am looking at the long term solution, where an IC in the 
PD gives the functionality we need for a robust and versatile system at 
low cost. My understanding of your proposal still puts a sense resistor 
and switch in the PD. I believe the size of the MOSFET does matter, not 
only in cost but in component space and heat sinking. I think there is
opportunity for savings in the PSE by putting the inrush in the PD and 
keeping the PSE switch small....maybe a SOT23 if we can get a vendor 
involved. In your approach, that can never happen.
>	[Yair Darshan]  We don't need design freedom where it is not
>required. 15W switching mode power supply working at the popular 100KHZ,
>does not need more than 470uF in its input. Guaranteed.
[Brian Lynch] 100kHz is popular today, and so is 500kHz and even 1MHz.
For ripple current capability, I agree that 470 is likely sufficient, 
but what-if a PD design wants to put in a larger cap for hold up time? 
Your definition has ruled out his doing so unless he adds complexity 
to his system (an isolation diode and a trickle charger, for example).
>	[Yair Darshan]  If you are referring to the isolating 
>switch, you don't need additional circuit. it works fine as presented. 
> The PD power supply will need the UVLO
>function in  any concept after the big cap, and you can have it free in
>commercial controller.
[Brian Lynch] I agree UVLO is free in most PWM controllers, but not
at the voltage thresholds a PD would want....not unless you add circuitry
>	[Yair Darshan]  I think you miss the point here, or you are in favor
>of putting the inrush current limiter in the PSE....., you can have delay
>function by adding a cap if you want, but it is not a must since we can
>allow the drop in the spec. In the circuit presented in March, there is no
>drop, the voltage is going down to around 20-30V.
>	We will have drop only if the isolating switch will work as a fast
[Brian Lynch] This is where it sounds like you are promoting current 
limiting in both the PSE and PD to split the power loss. 
If the PD MOSFET acts as a fast switch and the input voltage is 
allowed to "drop to zero" before charging the bulk capacitor then we get
into timing issues which I think are problematic in the long term.
>> [Brian Lynch] I the 350+/-50ma and 500ma +/-50ma are reasonable numbers. 
>> I think putting the inrush control in the PD side provides a more robust
>> solution that allows more design freedom and less opportunity for
>> mis-behavior.
>	[Yair Darshan]  I don't see how you reduce opportunity for
>miss-behavior, can you give some examples?
[Brian Lynch] I think that allowing the DC voltage to drop to zero and 
climb back to its final value during cap charging will cause complication 
in the PSE and in the PD and risks long term compatibility. The PD needs
energy storage to keep the switch ON and the PSE needs to know NOT to go 
into another re-discovery phase. more complexity......
If inrush limiting is in both the PSE and PD as you showed in March, then 
why bother with inrush limiting in the PSE at all? Save the MOSFET size
and the extra circuitry in the PSE. In the future, it is possible that an
integrated MOSFET in the PSE WILL be cheaper than a two IC solution if the
PSE switch is allowed to be small.
Let me try to summarize my view of the advantages of doing inrush 
limiting in the PD.
1) The switch in the PSE may be kept small. In the long term it may be 
cheaper to integrate into the controller. An alternative is to use a 
bipolar device as the switch. A SOT23 device is pennies.
2) The sizing of the switch in the PD is up to the PD designer. It can be
integrated, a SOT23 or a D2PAK. It is up to them to decide.
3) A discrete current limit circuit is possible in a low cost PD if a Vbe
junction is accurate enough.
3) The specifications of the behavior of the PSE and PSE are independent.
The timing of one size is not dependent on the other and the power
of one side is not dependent on the other. Both PSE and PD designers can
work in a well defined environment....a real benefit for reliability
4) There are no timing issues on startup. Tolerances in timing are 
transparent to the operation of the system. There is no doubt that so long
V-I characteristics are obeyed, the system will work every time.