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RE: PSE vs. PD power dissipation again

At the risk of repeating some of this discussion, let me summarize the 
PSE-PD dissipation issue as I see it. If I've made a mistake in any of the 
following points, please correct me!

We seem to be split into two camps:

Inrush limit by PD:
- No dissipation in PSE, which means we can integrate multiple switches
- Requires inrush circuit in PD = more $$ in PD (amount of $ subject to debate)
- Puts power dissipation in PD FET always = bigger PD FET
- Requires rapid overcurrent disconnect in PSE
- A PSE with this design cannot power up a PD with no inrush limit

Inrush limit by PSE:
- Requires big FETs in the PSE to survive 500mA/100ms wire short
- Can power any PD - with or without inrush protection
- Dissipation can be in PSE, PD, or shared
- Must allow extended over-current faults before turn-off - adds to PSE 
- Can power big PD cap faster (500mA vs 350) if the PSE is sized to 
dissipate the additional power

We need to endorse only one of these two, since they have mutually 
exclusive features.

Option 1 really only has one compelling feature, which is low watts in the 
PSE. We can integrate multiple option 1s in one chip. Multiple option 2s 
can't be integrated without some accommodation - sequential turn on, 
dynamically controlled current limit - something. There are secondary 
benefits to option 1 - it won't power up non-inrush-controlled PDs, which 
almost gets us the "second check" that Roger has been asking for, and it 
won't put a heavy load on a power-managed PSE for long durations during a 
wire short.

Option 2 has some nice features, most notably the ability to power up 
nearly any PD. It can also ride out a brief short on the wire without 
disconnecting the PD. A minor downside is that the PSE power supply must 
absorb a fair-sized overload if a PD classified as a low power device (with 
power allocated thusly) suffers a wire short. If we chose option 2, we 
encompass a wider range of PD designs, including some very low cost 
options. But it limits the ability to integrate multiple channels down the 

As an IC designer, I naturally favor option 1 - I'd like to sell PSE chips 
with many integrated channels. As an engineer, I'm willing to weigh the 
pros and cons of each (including ones I haven't thought of yet) and vote 
for the best solution. Let's continue to air out the pros and cons until 
Don's vote - coming soon, right, Don?