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RE: PSE vs. PD power dissipation again


I agree that we are in two camps, but I see the capabilities
slightly differently....see below


>-----Original Message-----
>From: Dave Dwelley [mailto:ddwelley@xxxxxxxxxx]
>Sent: Thursday, March 22, 2001 8:46 PM
>To: stds-802-3-pwrviamdi@xxxxxxxx
>Subject: RE: PSE vs. PD power dissipation again 
>At the risk of repeating some of this discussion, let me summarize the 
>PSE-PD dissipation issue as I see it. If I've made a mistake 
>in any of the 
>following points, please correct me!
>We seem to be split into two camps:
>Inrush limit by PD:
>- No dissipation in PSE, which means we can integrate multiple switches
>- Requires inrush circuit in PD = more $$ in PD (amount of $ 
>subject to debate)
[Brian Lynch] A low cost inrush limit could be a resistor and an NPN 
transistor. A .05 solution if you don't mind the temp co.

>- Puts power dissipation in PD FET always = bigger PD FET
[Brian Lynch] The dissipation in the FET is dependent on the current
through it, so if a PD designer wants to put in a small FET, all he has to
do is limit the current charging the capacitor - He has the option to scale
the capacitor and the FET to his application

>- Requires rapid over current disconnect in PSE
{Brian Lynch] Is this a bad thing?

>- A PSE with this design cannot power up a PD with no inrush limit
>Inrush limit by PSE:
>- Requires big FETs in the PSE to survive 500mA/100ms wire short
>- Can power any PD - with or without inrush protection
[Brian Lynch] I believe this is true to a point. By the definition Yair 
has presented, there is a start up time issue. If a PD takes too long to
start, the PSE may go back into discovery mode, or current limit. Remember,
the voltage drops at the PD when the bulk capacitor is connected so the 
PD has to have energy storage to ride through the time it has no power. 
If the PD id designed with inrush limiting to avoid the timing issue, 
then why bother with the big FET in the PSE?

>- Dissipation can be in PSE, PD, or shared
>- Must allow extended over-current faults before turn-off - 
>adds to PSE dissipation
>- Can power big PD cap faster (500mA vs. 350) if the PSE is sized to 
>dissipate the additional power
[Brian Lynch] In either case, the PSE can charge at 500ma if that is what we
decide it should do. This is independent of where the inrush limiting is.

>We need to endorse only one of these two, since they have mutually 
>exclusive features.
>Option 1 really only has one compelling feature, which is low 
>watts in the PSE. We can integrate multiple option 1s in one chip. Multiple

>option 2s 
>can't be integrated without some accommodation - sequential turn on, 
>dynamically controlled current limit - something. There are secondary 
>benefits to option 1 - it won't power up non-inrush-controlled 
>PDs, which 
>almost gets us the "second check" that Roger has been asking 
>for, and it 
>won't put a heavy load on a power-managed PSE for long 
>durations during a 
>wire short.
[Brian Lynch] I think it is also more robust. So long as the PD current 
limit is less than the PSE current limit, the system will work. There 
are no dependencies on timing or capacitor value as in the other case.
Also, the PSE always knows the what the load characteristics will be, and
the design solution can be optimized in the long term for lower costs. The
PD designer always knows the characteristics of it's input voltage, without
having to ride through intervals of no input during startup.
>Option 2 has some nice features, most notably the ability to power up 
>nearly any PD. It can also ride out a brief short on the wire without 
>disconnecting the PD. A minor downside is that the PSE power 
>supply must 
>absorb a fair-sized overload if a PD classified as a low power 
>device (with 
>power allocated thusly) suffers a wire short. If we chose option 2, we 
>encompass a wider range of PD designs, including some very low cost 
>options. But it limits the ability to integrate multiple 
>channels down the 
{Brian Lynch] Remember that the "almost any PD" is limited to a 
470uf capacitor on the front end. It also has to either have inrush 
limiting or the ability to ride through zero voltage input for a up 
to 100ms. More added cost to the very device that we are trying to 
save cost in....and the PSE is burdened with a big FET no matter what 
the load is.

>As an IC designer, I naturally favor option 1 - I'd like to sell PSE chips 
>with many integrated channels. As an engineer, I'm willing to 
>weigh the 
>pros and cons of each (including ones I haven't thought of 
>yet) and vote 
>for the best solution. Let's continue to air out the pros and 
>cons until 
>Don's vote - coming soon, right, Don?

[Brian Lynch] With or without a FET integrated into the PSE
controller, there is opportunity for a multi channel solution.