RE: PSE vs. PD power dissipation again
See my comments bellow.
Start-up voltage: Yair allows the PD to drop the line voltage below
threshold of 30 volts. All the state machine for the resistor
proposal have stated
that the PD should only draw power if the voltage is greater than
start-up. We can
allow this, but it creates a special start-up state.
I allow it, however it is not a must. You can use isolating switch scheme in
which the voltage at PD input is not drop to zero.
The isolating switch shown in my presentation is an example for such case.
No drops to zero.
Now, If we don't want to force specific implementation than we should allow
drop to zero for limited time.
Dieter is right that we should add special start up case. I agree, I don't
see a problem with it. Start up is special case regardless of the state
and should be specified at all specification levels.
Safety: With Yair's proposal, the PSE can not distinguish between a
fault and a
valid PD for the initial inrush time (50ms). This requires the PSE
to deliver over
1 joule before tripping. With PD current limiting the energy can be
mili-joules. This could allow some devices to survive. See my
message to Roger.
1. I don't see a problem for the PSE to deliver the power during that
time. In previous emails I have shown that there is no problems
for the component.
1.1 The issue of additional power required from the PSE during startup is
easily solved by PSE controller that will control when
to startup each port.Easy to do. This is part of the power management
that we are discussing.
1.2 It is not an safety issue, it is power dissipation issue for limited
time. Averaging it over system operating time gives zero. We are talking
about peak power
and we can handle it.
2. With PD inrush current the PSE switch deals with few mJoules but the PD
inrush current switch is taking the heat... could be over Joule too..
> -----Original Message-----
> From: Dieter Knollman [SMTP:djhk@xxxxxxxxxxx]
> Sent: ו, מרץ 23, 2001 8:55 PM
> To: Dave Dwelley
> Cc: stds-802-3-pwrviamdi@xxxxxxxx
> Subject: Re: PSE vs. PD power dissipation again
> Good summary. There are two points I would like to add.
> Start-up voltage: Yair allows the PD to drop the line voltage below the
> threshold of 30 volts. All the state machine for the resistor proposal
> have stated
> that the PD should only draw power if the voltage is greater than
> start-up. We can
> allow this, but it creates a special start-up state.
> Safety: With Yair's proposal, the PSE can not distinguish between a fault
> and a
> valid PD for the initial inrush time (50ms). This requires the PSE to
> deliver over
> 1 joule before tripping. With PD current limiting the energy can be a few
> mili-joules. This could allow some devices to survive. See my message to
> Dave Dwelley wrote:
> > At the risk of repeating some of this discussion, let me summarize the
> > PSE-PD dissipation issue as I see it. If I've made a mistake in any of
> > following points, please correct me!
> > We seem to be split into two camps:
> > Inrush limit by PD:
> > - No dissipation in PSE, which means we can integrate multiple switches
> > - Requires inrush circuit in PD = more $$ in PD (amount of $ subject to
> > - Puts power dissipation in PD FET always = bigger PD FET
> > - Requires rapid overcurrent disconnect in PSE
> > - A PSE with this design cannot power up a PD with no inrush limit
> > Inrush limit by PSE:
> > - Requires big FETs in the PSE to survive 500mA/100ms wire short
> > - Can power any PD - with or without inrush protection
> > - Dissipation can be in PSE, PD, or shared
> > - Must allow extended over-current faults before turn-off - adds to PSE
> > dissipation
> > - Can power big PD cap faster (500mA vs 350) if the PSE is sized to
> > dissipate the additional power
> > We need to endorse only one of these two, since they have mutually
> > exclusive features.
> > Option 1 really only has one compelling feature, which is low watts in
> > PSE. We can integrate multiple option 1s in one chip. Multiple option 2s
> > can't be integrated without some accommodation - sequential turn on,
> > dynamically controlled current limit - something. There are secondary
> > benefits to option 1 - it won't power up non-inrush-controlled PDs,
> > almost gets us the "second check" that Roger has been asking for, and it
> > won't put a heavy load on a power-managed PSE for long durations during
> > wire short.
> > Option 2 has some nice features, most notably the ability to power up
> > nearly any PD. It can also ride out a brief short on the wire without
> > disconnecting the PD. A minor downside is that the PSE power supply must
> > absorb a fair-sized overload if a PD classified as a low power device
> > power allocated thusly) suffers a wire short. If we chose option 2, we
> > encompass a wider range of PD designs, including some very low cost
> > options. But it limits the ability to integrate multiple channels down
> > road.
> > As an IC designer, I naturally favor option 1 - I'd like to sell PSE
> > with many integrated channels. As an engineer, I'm willing to weigh the
> > pros and cons of each (including ones I haven't thought of yet) and vote
> > for the best solution. Let's continue to air out the pros and cons until
> > Don's vote - coming soon, right, Don?
> > Dave << File: Card for Dieter Knollman >>