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I'd like to suggest that the management ad-hoc and all interested people, take up
the task of defining an interface physical layer spec for the PSE port chip.
1) Because there would be more competition if we standardize it, like 10 gig did (or is doing)
with the 4 x 2.5 gig serial busses.
2) If we leave the I/O as single function pins on the chip, then there will be a lot of pins at the PSE controller.
3) a spec will help as we go to duals, quads, etc, where one interface can be used for all ports within a package
4) When it comes time to start ordering these PSE chips, this part of the chip will have some physical definition
5) ... and because the discovery ad-hoc reflector is getting all of the traffic
One suggestion would be to use some kind of serial bus, like I2C.
High processing speed is not needed here.
Some I/O to be considered, for example:
PSE port chip inputs:
enable discovery 1 bit
enable classification 1 bit (optional)
enable DTE power 1 bit
reset 1 bit (optional)
PSE port chip outputs:
discovery successful 1 bit
classification value 2-3 bits (optional)
power is good 1 bit (10ma <= current <= 350 ma)
over-current fault 1 bit
under-current (unplug) 1 bit
over-voltage fault 1 bit ?? needed ??
output current 8-12 bits (optional)
output voltage 8-12 bits (optional, probably not needed anyway)
PD signature too high 1 bit ?? needed ??
PD signature too low 1 bit ?? needed ??