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FW: Inrush limiting - PSE or PD - Revisited

Title: FW: Inrush limiting - PSE or PD - Revisited

This message is from Brian Lynch at TI, his pdf file was too big for the ad-hoc reflector.
So, I sent it to David Law, who kindly put it in the documents folder.

I am forwarding this email to let everyone know that Brian's file is located at:

Please refer to this file along with the text below.

- Rick

-----Original Message-----
From:   Lynch, Brian
Sent:   Wednesday, May 02, 2001 11:58 AM
To:     stds-802-3-pwrviamdi@xxxxxxxx
Subject:        Inrush limiting - PSE or PD - Revisited


Just after the last meeting in Hilton Head, there was a flurry of Email on the reflector regarding inrush current limiting, and where it should be placed: The PSE or the PD.

Since then, I have put together two simulations. The first showing operation with inrush limiting in the PSE (Method A) , and the second with inrush limiting in the PD (Method B). The first page of the attached .pdf files shows the schematic used for Method A. (The circuit for Method B is similar. I have left it out to keep the file small. I 'll send a copy if requested.)

In both cases, there is a PSE which includes a bulk power source and a switch in series to connect it to the PD after discovery. In the PD there is a DC/DC converter, separated from the PSE by a switch and an circuitry to control that switch.. The DC/DC converter is modeled as an average model to speed up simulation time. The load resistor at the far right is used to vary the power required by the PD.

I wanted to share my findings with the group before the meeting later this month in St.Louis, so that (hopefully) we can come to a conclusion. If anyone is interested in seeing more wave forms from my simulations, let me know. I have not included too many of them here because of file size limitations.

During the discovery/classification process, there is a requirement that the capacitance across the power lines be limited to a small value. This is in contrast to the need of the follow on DC/DC converter, which requires a relatively large capacitance at its input. To accommodate both requirements, a "switch" is placed in series with the input line in the PD. This switch disconnects the capacitor from the PSE during detection/classification, and connects it, and the DC/DC converter, to the PSE for normal powered operation.

When the switch is closed and the capacitor is initially connected, there is a large inrush of current into the bulk capacitor as it charges. The following is a comparison of two methods to manage this inrush current. In addition, the circuits used in each method must protect themselves and connected equipment from failure in the event of a fault occurring.

Method A: Inrush limiting in PSE.

Method B: Inrush limiting in the PD

In both approaches, I assume the DC/DC converter has its own current limit circuit. This means that if a fault in the load occurs, the DC/DC converter will limit the power to the fault. It may be any type of current limit (self resetting, latch off, or any type the PD designer wants to use).

Observation in operation: I looked at three modes of operation: Startup, A short circuit on in the Ethernet wiring, and  finally a short between the switch and the DC/DC converter ( a shorted Bulk Capacitor).

1) Startup: This is when the PSE switch FET turns ON and the output voltage increases from detection/classification to full ON 44 to 57 volts. When the voltage at the PD reaches this regulation, the switch in the PD turns ON.

Method A.

Method B.

NOTE: During simulations, it was observed that Method A needed to start in as short a time to guarantee operation. This limits losses in the event of a fault, but also limits the size of the bulk capacitor used in the PD. Timing of events was critical to operation.

By contrast, in Method B, startup time had no effect the systems ability to start. Whether the time was long to reduce peak power loss, or very short, the system would always start.

2) Shorted wiring: In this operating condition, I am assuming a failure has taken place, which puts a short on the Ethernet cabling.

Method A:

Method B:

3) Shorted bulk capacitor: In this operating condition, I am assuming a short has been placed across the bulk capacitor; between the DC/DC converter and the PD switch FET.

Method A:

Method B:
The PD detects an increase in current while the voltage on the bus has gone to
zero. The PD then enters a low power mode similar to that of turn ON.

In either Case 2 or Case 3, the PSE will determine that the PD has gone away, and will react accordingly.

Design considerations: When implementing these both circuits in simulations, I noted some of the design considerations, considering PDs ranging in power from ~ 1 watt to the full ~13 watts.

Method A:

c) PD switch FET has limited power dissipation and can be small.

Method B:

        of the bulk capacitor to say, 100ma, peak power dissipation in the PD switch    PET can be significantly reduced (at the expense of a longer capacitor charge   time)

I know this is long, but I hate to think of us getting too far behind on some of the issues.  Any comments from others?

Brian T. Lynch
Principal Member of Applications Development
Power Supply Control Products
Texas Instruments Incorporated
                                                       +  brian_lynch@xxxxxx
7 Continental Boulevard                      ( 603 429 6054
Merrimack, NH 03054-4303                2  603 429 8564