Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

RE: Inrush limiting - PSE or PD - Revisited

Brian and all,
Thanks for revisiting this issue again.
Attached my comments.



> -----Original Message-----
> From:	Rick Brooks [SMTP:ribrooks@xxxxxxxxxxxxxxxxxx]
> Sent:	ו, מאי 04, 2001 3:48 PM
> To:	stds-802-3-pwrviamdi@xxxxxxxx
> Subject:	FW: Inrush limiting - PSE or PD - Revisited
> This message is from Brian Lynch at TI, his pdf file was too big for the
> ad-hoc reflector. 
> So, I sent it to David Law, who kindly put it in the documents folder. 
> I am forwarding this email to let everyone know that Brian's file is
> located at: 
> <> 
> Please refer to this file along with the text below. 
> thanks. 
> - Rick 
> -----Original Message----- 
> From:   Lynch, Brian 
> Sent:   Wednesday, May 02, 2001 11:58 AM 
> To:     stds-802-3-pwrviamdi@xxxxxxxx 
> Subject:        Inrush limiting - PSE or PD - Revisited 
> All, 
> Just after the last meeting in Hilton Head, there was a flurry of Email on
> the reflector regarding inrush current limiting, and where it should be
> placed: The PSE or the PD.
> Since then, I have put together two simulations. The first showing
> operation with inrush limiting in the PSE (Method A) , and the second with
> inrush limiting in the PD (Method B). The first page of the attached .pdf
> files shows the schematic used for Method A. (The circuit for Method B is
> similar. I have left it out to keep the file small. I 'll send a copy if
> requested.)
> In both cases, there is a PSE which includes a bulk power source and a
> switch in series to connect it to the PD after discovery. In the PD there
> is a DC/DC converter, separated from the PSE by a switch and an circuitry
> to control that switch.. The DC/DC converter is modeled as an average
> model to speed up simulation time. The load resistor at the far right is
> used to vary the power required by the PD.
> I wanted to share my findings with the group before the meeting later this
> month in St.Louis, so that (hopefully) we can come to a conclusion. If
> anyone is interested in seeing more wave forms from my simulations, let me
> know. I have not included too many of them here because of file size
> limitations. 
> Background: 
> During the discovery/classification process, there is a requirement that
> the capacitance across the power lines be limited to a small value. This
> is in contrast to the need of the follow on DC/DC converter, which
> requires a relatively large capacitance at its input. To accommodate both
> requirements, a "switch" is placed in series with the input line in the
> PD. This switch disconnects the capacitor from the PSE during
> detection/classification, and connects it, and the DC/DC converter, to the
> PSE for normal powered operation.
> When the switch is closed and the capacitor is initially connected, there
> is a large inrush of current into the bulk capacitor as it charges. The
> following is a comparison of two methods to manage this inrush current. In
> addition, the circuits used in each method must protect themselves and
> connected equipment from failure in the event of a fault occurring.
> Method A: Inrush limiting in PSE. 
> Here, the PSE current limiting is set at a level below that in PD. This
> means that a PD will draw as much current as it is allowed by the PSE.
> During startup, a PSE allows current flow of up to 500ma for 100ms, then
> current limits at 350ma for continuous operation. During the time the PSE
> is in current limit, the bus voltage drops to the level required to
> maintain the maximum current. If current exceeds either current limit
> point, the PSE will shut down and re-enter discovery mode.
> Method B: Inrush limiting in the PD 
> Here, the PD current limit is set below that in the PSE. This means that a
> PD will limit its own current to a level necessary to maintain the bus
> voltage at its proper level. During startup, the PD limits current to less
> than 500ma for 100ms, and limits at 350ma thereafter. The PSE only limits
> current if there is a fault (short, or mis-wiring) between the PSE and the
> PD.
> In both approaches, I assume the DC/DC converter has its own current limit
> circuit. This means that if a fault in the load occurs, the DC/DC
> converter will limit the power to the fault. It may be any type of current
> limit (self resetting, latch off, or any type the PD designer wants to
> use).
> Observation in operation: I looked at three modes of operation: Startup, A
> short circuit on in the Ethernet wiring, and  finally a short between the
> switch and the DC/DC converter ( a shorted Bulk Capacitor).
> 1) Startup: This is when the PSE switch FET turns ON and the output
> voltage increases from detection/classification to full ON 44 to 57 volts.
> When the voltage at the PD reaches this regulation, the switch in the PD
> turns ON.
> Method A. 
> In Method A. the PD switch turns ON fully immediately. Thus, there is a
> time where the bus voltage will drop as the bulk capacitor in the DC/DC is
> charged.. To keep the switch in the PD ON, we need to add switched in
> energy storage at PD - The PD needs to stay alive for a period of time
> while the input goes away and slowly returns. This storage cannot be there
> during detection, therefore the cap must be switched in at >30 volts. The
> size of this capacitor should be large enough to sustain the PD control
> circuit during this interval, yet small enough to that charging it does
> not add significantly to the overall startup time. 10uf?
> The PSE switch FET is turned ON in a linear fashion, so the turn on
> dissipation is in the PSE FET in this method. 
> Also, there needs to be an accurate Under Voltage Lock Out (UVLO) in the
> DC/DC converter. The DC/DC must stay off until the voltage is completely
> up, otherwise the system will not start. This is especially true of higher
> powered PDs.
> Lastly, there is a timer required in PSE to determine whether there is a
> fault, or startup condition. (more on faults later)
> Page two of the attached .pdf file shows (starting at the bottom) the
> input to the PD in blue, and the voltage on the bulk capacitor. the
> initial "bumps" in the wave form are the voltages seen by the PD during
> Discovery and classification. At about 40ms the switch on the PSE is
> closed, and the voltage rises abruptly. Moments later, the switch on the
> PD closes and the voltage drops, and then gradually increases as the bulk
> capacitor charges. The top trace, in green, shows the DC/DC converter
> powering up as soon as the capacitor voltage reaches 44 volts.
> Lastly, the middle trace shows the current delivered by the PSE during
> startup. 
> Page three shows the power dissipated in the PSE and PD switch
> they are turned on and the bulk capacitor is charged.
> Method B. 
> In this method, the switch in the PSE turns ON quickly, and the PD FET
> turns ON in a linear mode, limiting the current to a value determined by
> the PD designer. When the voltage ramps up on the bulk capacitor, the PD
> FET turns fully ON. In this method, the startup power dissipation is in
> the PD FET.
> The DC/DC converter may be held OFF during the charging of the capacitor,
> or may be allowed to turn ON. If left to turn ON, the turn on time
> increases and the dissipation in the series FET increases for that period
> of time it takes the capacitor to charge.
> Page three of the attached .pdf file shows the input to the PD, the bulk
> capacitor voltage, the PSE current, and the DC/DC converter's output
> voltage. 
> In this simulation, the PD enables the DC/DC converter when the capacitor
> is charged, and so no UVLO circuitry is required. Also, the PD charges the
> capacitor with a lower current than full load operating current (about
> 175ma here) to keep power dissipation low in the PD switch.
> Page four shows the power loss in the PSE and PD switches during power ON.
> The PSE switch power dissipation is negligible, and the PD switch loss is
> less than that seen in Method A. A further decrease in power loss could be
> accomplished at the expense of a longer capacitor charging time.
> NOTE: During simulations, it was observed that Method A needed to start in
> as short a time to guarantee operation. This limits losses in the event of
> a fault, but also limits the size of the bulk capacitor used in the PD.
> Timing of events was critical to operation.
> By contrast, in Method B, startup time had no effect the systems ability
> to start. Whether the time was long to reduce peak power loss, or very
> short, the system would always start.
	[Yair Darshan]  
              The PD power supply input capacitor is needed to be limited to
470uF or so. It is actually not a problem since a 15W switching mode power
              doesn't need more than 300-400uF for a standard low cost
100Khz design. Thus limiting the PD input cap is easy requirement.

		If we insist that the PD designer should have the freedom to
use 100,000uF or more in his PD, in this case he can add if he wants 
            an inrush current limit in his PD. 
		I am assuming that 99% of the applications are applications
that is using no more than 15W switch mode power supply.

            In any case, method A does not cause startup problems if the PD
cap is to big. In this case it will take more time to charge up the PD cap. 
           as it would in method B.  
          2) Shorted wiring: In this operating condition, I am assuming a
failure has taken place, which puts a short on the Ethernet cabling.

> Method A: 
> 	The PSE switch stays ON, delivering 350ma for 100ms, with up to 57
> volts across it. ~20 watts until the PSE decides there is a fault and
> shuts OFF.
> 	Additional circuitry could be added to the PSE which would monitor
> whether the bus voltage had once been valid for a time, and has become
> invalid due to a short.
> Method B: 
> 	If the wiring shorts, the PSE delivers 350ma for 50us or so, then
> shuts off. The result is the same power dissipation for a much shorter
> period of time.
> 3) Shorted bulk capacitor: In this operating condition, I am assuming a
> short has been placed across the bulk capacitor; between the DC/DC
> converter and the PD switch FET.
> Method A: 
> 	Since the PD switch is fully ON, there is a small difference in
> dissipation in the PD switch FET.  In operation, if the PD controller
> loses its bias power, and shuts OFF the FET. The PD goes to zero power and
> the PSE enters discovery mode. Otherwise, the PSE will time out and
> dissipation is the same as in Case 2.
> Method B: 
> The PD detects an increase in current while the voltage on the bus has
> gone to 
> zero. The PD then enters a low power mode similar to that of turn ON. 
> In either Case 2 or Case 3, the PSE will determine that the PD has gone
> away, and will react accordingly. 
> Design considerations: When implementing these both circuits in
> simulations, I noted some of the design considerations, considering PDs
> ranging in power from ~ 1 watt to the full ~13 watts. 
> Method A: 
> 	a) PSE dissipates power during startup and faults. PSE sizes FET for
> worst case, not knowing what PD will be used. The time to shut OFF is
> subject to the size of the bulk capacitor being used in the PD.
		[Yair Darshan]  

		Since in method A we limits the PD cap to 470uF or so, the
time to shut off in case of fault is known.
> 	b) PD designer needs a startup circuit for the PD control circuitry.
> The storage in the PD must be long enough to keep the PD alive during
> startup. 
		[Yair Darshan]  We did it with less than 1uF cap in the
isolating switch that works as fast switch in order not to dissipate power.
		                        In other application, as presented
in March, the isolating switch was implemented by two resistors and Mosfet
with out any storage circuits.
						It is a meter of
implementation, not a real problem. 

> c) PD switch FET has limited power dissipation and can be small. 
	[Yair Darshan]  What will be the case in high/medium power PD's?.
You can set the inrush current limit to low value, however, after startup
you need to change 
				      the threshold to higher value to allow
operation. And how you handle peaks, noise load changed etc. You need more
components to handle this.
		 			You have these hardware already in
the PSE.

					In addition, for high capacitance,
you can not pick to low current other wise the charging time will be so long
that the user of the PD will not know 
	                        if his PD working or is faulty. We need to
define what is acceptable time to get service, i.e. operation of the PD.

			            In method A you don't have this
			            The PSE supply 500mA for 100mSec.
					Afterwards you have 350mA
			            The PD input cap is limited to 470uF.

					Knowing the above resources, the PD
designer should use standard procedures to design his PD power supply. 

> 	d) PD designer needs to insure DC/DC converter is OFF until bulk
> capacitor is charged, otherwise the circuit will not start.
		[Yair Darshan]  It is true for all methods. 

> 	e) The PD designer is limited to the size of the bulk capacitor used
> in the PD. Too large, and the PSE wll time out and the system will not
> start
		[Yair Darshan]  The concept of Method A is that the PD input
cap value will be limited. It will help in prevent PSE-PD inter operate
		                        I see in limiting this cap. as
important advantage and not a drawback.  

> 	f) You can always add inrush limiting to the PD to limit the FET
> size. In effect, if we specify Method A, then Method B could always be
> implemented to insure startup operation. The down side is that the PSE is
> now severely oversized.
		[Yair Darshan]  If you add inrush current limiting in the
PD, you increase FET size in PD! 
		                       In addition, you add hardware that
you have anyway in the PSE.
						THE point of method A is
that you will never need inrush current limit in the PD.
> Method B: 
> 	a) PSE power dissipation is small, so the FET may be kept small for
> any application. 
		[Yair Darshan]  Correct. However the MOSFET in the PD will
be bigger that in method A.
> 	b) PD designer has freedom to scale his FET size, based on his bulk
> capacitor size and power level in his own application. 
		[Yair Darshan]  Correct. This freedom allow some reduction
in the FET size in the PD for some of the applications, However it adds
additional circuit to the PD
		                        and complicate its design.
		                        If we are looking at the cost issue:
		                        PSE FET SIZE (METHOD A) - PSE FET
SIZE (METHOD B) >> PD inrush current limit circuit.

> 	c) Circuit operation voltage and current dependent is independent of
> circuit time constants.
		[Yair Darshan]  If PD cap is limited in value, it is the
same as Method A. If it is not limited in size it will be highly dependent
on the implementation 
		                        of the inrush current limit in the
PD and a lot more (Soft start, under voltage lockout etc.) while in method A
you don't have this problems at all. 
> 	d) In practice, the inrush current limit in the PD will be set much
> lower than 350ma. (or the 500ma for 100ms for that matter). By setting the
> charging current 
>         of the bulk capacitor to say, 100ma, peak power dissipation in the
> PD switch    PET can be significantly reduced (at the expense of a longer
> capacitor charge   time)
	[Yair Darshan]  What will be the case for high/medium power PD's
when the operating current is greater than the inrush current setting
	                        In this case you will need to level inrush
current limiter , and timing circuits etc. ... more cost.

> I know this is long, but I hate to think of us getting too far behind on
> some of the issues.  Any comments from others? 
	[Yair Darshan]  

> Brian T. Lynch 
> Principal Member of Applications Development 
> Power Supply Control Products 
> Texas Instruments Incorporated 
>                                                        *
> brian_lynch@xxxxxx 
> 7 Continental Boulevard                      * 603 429 6054 
> Merrimack, NH 03054-4303                *  603 429 8564