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RE: Potential heating problem



Title: RE: Potential heating problem

Jack,
you are correct in that we do not know the cause of these failures.
I'm hoping that people who know can describe the failure mode.

It is rather easy to design a board with 3 or 4 mil traces on 1/2 oz copper that is:
100 ohm differential, and less than 0.3 ohms series R, and that will also be damaged with 100 to 300ma of continuous current.

Whereas using 8 mils or wider traces would not have a problem with the current.
So, we cannot rule out trace width as a cause. Of course, over etch can be a big problem with narrow traces.

What Sterling said is there is a spec for resistance through the patch panel.
It sounds like there is no a spec for current handling capacity?
So, like Dan Dove and others have said, we need a survey of what is in the installed base.

Perhaps we should revisit the topic from the Liaison Letter (May 2000 interim meeting)
http://www.ieee802.org/3/af/public/may00/tr42_liaison.pdf

where it stated:
PCB:
* CEI IEC 60603-7: current capacity for connectors @20 C - 1.8 A (@ 0 C -2.2
A, @ 40 C - 1.4 A, @ 60 C - .75 A)

which implies that compliant patch panels will not have a problem with 350ma.
Can we get TR-42 to take a survey of the installed base?

- Rick