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you are correct in that we do not know the cause of these failures.
I'm hoping that people who know can describe the failure mode.
It is rather easy to design a board with 3 or 4 mil traces on 1/2 oz copper that is:
100 ohm differential, and less than 0.3 ohms series R, and that will also be damaged with 100 to 300ma of continuous current.
Whereas using 8 mils or wider traces would not have a problem with the current.
So, we cannot rule out trace width as a cause. Of course, over etch can be a big problem with narrow traces.
What Sterling said is there is a spec for resistance through the patch panel.
It sounds like there is no a spec for current handling capacity?
So, like Dan Dove and others have said, we need a survey of what is in the installed base.
Perhaps we should revisit the topic from the Liaison Letter (May 2000 interim meeting)
where it stated:
* CEI IEC 60603-7: current capacity for connectors @20 °C - 1.8 A (@ 0 °C -2.2
A, @ 40 °C - 1.4 A, @ 60 °C - .75 A)
which implies that compliant patch panels will not have a problem with 350ma.
Can we get TR-42 to take a survey of the installed base?
From: Jack Andresen [SMTP:jandresen@xxxxxxxxxx]
Sent: Tuesday, May 08, 2001 10:58 AM
To: Schwartz, Peter
Cc: Sterling Vaden; stds-802-3-pwrviamdi@xxxxxxxx
Subject: Re: Potential heating problem
With Stirlings high current tests and all the analysis by others, I
believe that trace size is not the culprit we seek.
The fact that several people have reported failures is very important.
What other mechanisms could explain the failures? The failure of same
boards may be due to a variety of other causes. A couple,
1) Poor interconnection. i.e. a high resistance connection, RJ plug to
2) Poor PCB plating. A high resistance through hole connection.
Anybody have other ideas?
"Schwartz, Peter" wrote:
> Perhaps the rather handy little calculator available for free download form
> this website will help you out. The specific file of interest is
> http://www.contrive.it/Download.html <http://www.contrive.it/Download.html>
> Peter Schwartz
> Applications Engineer
> Micrel Semiconductor
> Phone: 408.435.2460
> FAX: 408.456.0490
> -----Original Message-----
> From: Jack Andresen [SMTP:jandresen@xxxxxxxxxx]
> Sent: Monday, May 07, 2001 13:22
> To: Sterling Vaden
> Cc: Dave Dwelley; stds-802-3-pwrviamdi@xxxxxxxx
> Subject: Re: Potential heating problem
> To understand your figures. Your traces are 1.4 mils thick because
> are internaland have no overcoat, correct?. The traces are 10 mils
> but how long and how much space between traces.
> By my calculations, your traces have about .75 ohms per foot. I get
> ohms from your stated voltage drop and the current.So the total
> of your traces is about 6.9 inches. Am I in the ball park?
> With your total of 2.95 Watts, the equivalent surface are is about
> sq in. with your 60 degree C over ambient, However, you say the
> temperature is 90 to 107. How can the surface temperature be higher
> the temperature source, namely the PC traces. Please explain
> Jack Andresen
> Sterling Vaden wrote:
> > I have been running a little informal test of current carrying
> capacity. I
> > am currently (get it) running 2.6 Amperes through a pair of traces
> (.010 X
> > .0014) wired in series, embedded in the inner layers, one directly
> above the
> > other, of the test board shown. The temperature rise is
> approximately 60
> > degrees C over ambient yielding 98 to 107 C as measured on the
> surface of
> > the pcb. No discoloration of the board material has been noted.
> The traces
> > are dissipating 1.138 X 2.60 = 2.96 W. No catastrophic failure has
> > noted.
> > Now. I predict that if traces are failing at .250 A, those must be
> > traces indeed!
> > Sterling Vaden
> > Dave Dwelley wrote:
> > > Do these miniature traces affect our 20 ohm wiring budget?
> > >
> > > What's the typical DC resistance of a patch panel?
> > >
> > > Dave Dwelley
> > >
> > > Jack Andresen wrote:
> > >
> > > >But let me go back to original issue. I have looked at many
> patch panel
> > > >PC boards and for various reasons, the traces run from 10 to 18
> > > >Possible reasons:
> > > >1) Making pairs of traces 100 ohm. 2) Trying to get between the
> > > >pins. 3) Running a pair between the 110 punch down pins. 4) In
> > > >there is very little space for both compensation and wiring
> > > >leaving margins between pairs of traces. 5) People are afraid
> of too
> > > >fine traces
> > > >But it is important to recognize here is no general standard
> for patch
> > > >panel traces (as pointed out in one of the responses).
> > Name: pcbCurrentCapacity.doc
> > pcbCurrentCapacity.doc Type: Winword File
> > Encoding: base64