RE: insuring the stability of power delivery
Rick and all,
See my comments below.
> -----Original Message-----
> From: Rick Brooks [SMTP:ribrooks@xxxxxxxxxxxxxxxxxx]
> Sent: ה, מאי 31, 2001 1:02 AM
> To: stds-802-3-pwrviamdi@xxxxxxxx
> Subject: insuring the stability of power delivery
> I just wanted to voice one concern that I have regarding power ramp up,
> and continuous power modes.
> I was reminded of this issue when I was simulating the current limits in
> the PSE and PD and watching
> oscillations on the cable during startup. Yair's Pspice circuit does not
> have these problems
> due to the fact that there are Op-amps in the current limit feedback loops
> (i.e. band limited).
[Yair Darshan] Correct, in a typical design, the bandwidth is
limited, thus preventing oscillation.
If you are using behavioral models that are
not limited in bandwidth, you should expect oscillations.
In my model I have used real
circuit model which is bandwidth limited, therefore, no oscillations.
> It seems to me that we do not yet have a defined and specified behavior
> that will insure that the DTE power will be
> delivered in a stable way.
> How do we guarantee that a PD from vendor "A" will not oscillate when
> connected to a PSE from vendor "B"?
> The PD as an electrical load needs to be dominated by a capacitive
> I think that we all agree, but this has not yet been specified.
[Yair Darshan] I agree that we need to specify "something" to
insure inter-operate, however it is not an easy task since a lot more
The PD is not just a capacitive load, it is
also a load with negative resistance which is frequency depended and has
poles and zeros at its
reflected input impedance.
Your point is equivalent to the
following question: How a manufacture of standard switching power supply
ensure that his power supply will be stable when it is delivering power to a
load that is also a dc/dc switching converter. There are no standards for
this issue since the number of application and scenarios are un limited.
However, there are some "golden" rules that help to minimize those problems.
1. Keeping low ratio of L/C . L is the line inductance. C is the
input capacitor of the load (PD power supply input.) It means relatively
large capacitance at PD power supply input.
2. The total impedance's of the source output and the load input
should be positive (hard to define but possible)
3. Add some series loss to the cable (resistor).
> During power ramp up, either the PSE or PD current limit will be in
> effect, so we need to specify the behavior
> during power ramp up.
[Yair Darshan] If you have current limit at the PSE, you solve most
of the problem since you have one side with limited bandwidth and the most
important thing is
that you put dissipative element in series to the cable that damps
the oscillations very rapidly or prevent them from starting. (Meets rule 3
> At the present time, what behavior is specified to insure that the PSE
> feedback loops,
> either to regulate the output voltage, or to limit the current (protection
[Yair Darshan] Limit the PSE output current is the most effective
> will not oscillate with the longest UTP cable or the PD?
> It seems that we need to address these issues or we do not have a complete
If we specify that the PSE have a current limit (which we did
already) we have 90% of the solution. In this case the PD will need to meet
design rules that do not need to be specified. In any case we should
analyze this concept under some typical operational envelope that should
include the following parameters:
PSE output current limit bandwidth which is unconditionally stable.
PD min. input capacitor
Cable max. inductance.
> Some ideas:
> 1) specify the maximum loop bandwidths of the PSE and PD loops so that any
> such system will always
> behave as a lumped circuit. In other words, spec the loop bandwidth so
> that it is about 6 to 10
> times smaller than 1/lambda of the maximum length UTP cable.
> We do not want sudden load changes to cause oscillation or ringing, for
> Slew rate helps, but it is a large signal behavior only.
> 2) specify a minimum phase margin into a "standard" PD load (whatever that
> 3) specify a maximum gain at the UTP bandwidth at the longest cable.
> 4) both the PSE and PD need to have a specified behavior.
> Any other ideas or discussion on this topic?
> How about you power guys???
[Yair Darshan] See above.
> - Rick