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RE: insuring the stability of power delivery

Title: RE: insuring the stability of power delivery

you bring up some good points, and you echo some of my concerns.

First of all, my opinion is that there are 5 different states of operation:

1) Discovery of 25K slope, the behavior is well accepted at this point
        2.8V to 10V delta of 2V min, PD is +/-5%, discovery time is xx ms, etc...
        the max allowed load cap is about 0.7uF (PSE and PD)

2) Classification
        it is optional for both PSE and PD
        it is done at 15V to 20V, and from 5ma to 40ma (roughly) depending on the class
        it is done only after the discovery portion for the protection of legacy devices, hazard matrix, etc...
        the max allowed load cap is also probably about 0.7uF (PSE and PD)

3) Power Ramp Up
        there is some kind of UVLO with hysteresis, Yair's numbers are mostly accepted
        PSE and PD both manage the startup current
        0.5A is the max current for xx ms
        the max cap load is now 50uF, higher values require PD circuitry to buffer (to be defined)

4) Continuous Power Delivery
        the load current is between 10ma and 350ma
        the PD max power is 12.95W, the PSE min available power is 15.4W
        the PSE puts out between 44V and 57V
        I think that we need to add bandwidth of interest and spec the allowed loads, e.g. cap loads

5) Power Ramp Down
        occurs due to unplug after xx ms
        occurs due to an over-current or other fault
        must return to the discovery process before power can be applied again

To start with, these states each contain behavior that is unique to that state,
the behavior is then simplified between different states if possible.

My last email concerned only power ramp up and continuous delivery, not classification.

I agree, I do not think that we can get "perfect" stability, but we should decide on some performance goals.
We do not want a compliant PD to oscillate so that the voltages and current are driven outside of the proper
bounds therefore resulting in the power turning off.
It can be difficult to design a PSE output that is stable into any load, right?
Phase and gain margins are one way to define stability.
We could devise a separate test fixture for both the PSE and PD to test for compliance.

A purely resistive load should be easy, where the min cap is close to zero.
A large cap/res load is rather easy, except for huge cap values.
Again, large cap values are possible if the PD provides the proper load to the PSE.
Constant power loads (negative resistance loads) with caps can be harder to control and specify,
these types will account for most of the loads we will have (IP phones, etc...)

I just want us to figure out what we need to do to guarantee interoperability, otherwise, the standard
may not succeed.

- Rick