----- Original Message -----
Sent: Thursday, May 31, 2001 3:27
Subject: RE: insuring the stability of
you bring up some good points, and you echo some of my
First of all, my opinion is that
there are 5 different states of operation:
1) Discovery of 25K slope, the
behavior is well accepted at this point
2.8V to 10V delta of 2V min, PD is +/-5%, discovery time is xx ms,
the max allowed load cap is about 0.7uF (PSE
it is optional for both PSE and PD
it is done at 15V to 20V, and from 5ma to 40ma (roughly) depending on
it is done only after the discovery portion
for the protection of legacy devices, hazard matrix, etc...
the max allowed load cap is also probably about 0.7uF (PSE and
3) Power Ramp Up
there is some kind of UVLO with hysteresis, Yair's numbers are mostly
PSE and PD both manage the startup
0.5A is the max current for xx ms
the max cap load is now 50uF, higher values require PD circuitry to
buffer (to be defined)
4) Continuous Power Delivery
the load current is between 10ma and 350ma
the PD max power is 12.95W, the PSE min available power is 15.4W
the PSE puts out between 44V and 57V
I think that we need to add bandwidth of interest and spec the allowed
loads, e.g. cap loads
5) Power Ramp Down
occurs due to unplug after xx ms
occurs due to an over-current or other fault
must return to the discovery process before power can be applied
To start with, these states each
contain behavior that is unique to that state,
the behavior is then simplified between different states if
My last email concerned only power
ramp up and continuous delivery, not classification.
I agree, I do not think that we can
get "perfect" stability, but we should decide on some performance
We do not want a
compliant PD to oscillate so that the voltages and current are driven outside
of the proper
therefore resulting in the power turning off.
It can be difficult to design a PSE output that is stable
into any load, right?
and gain margins are one way to define stability.
We could devise a separate test fixture for
both the PSE and PD to test for compliance.
A purely resistive load should be
easy, where the min cap is close to zero.
A large cap/res load is rather easy, except for huge cap
Again, large cap
values are possible if the PD provides the proper load to the PSE.
Constant power loads (negative
resistance loads) with caps can be harder to control and specify,
these types will account for most of
the loads we will have (IP phones, etc...)
I just want us to figure out what we
need to do to guarantee interoperability, otherwise, the standard
may not succeed.
Sent: Thursday, May
31, 2001 3:40 AM
To: Brooks, Rick [SC5:321:EXCH]; stds-802-3-pwrviamdi
Subject: Re: insuring the stability of power delivery
Your questions are all good.
But I believe this over laps some what with the classification process. (Or
maybe I am just sensitive because of a real world situation that I have
Recently I have been made aware of a situation at
an end user site. The PD, (and I use this term loosely to put it in terms of
the groups discussion), equipment was specified as watt load of X watts by
Manufacturer A. The power engineering was done for Manufacturer B's
equipment. It was determined that a system of Y watts was required to hand
X*Z loads. (The system actually had 2*Y capacity) Yet in reality during
the start up phase of the system the real requirement for power delivery was
Unofficial investigation showed that indeed
Manufacturer A load specification was as stated, except during startup. During
start up the system exhibited a large capacitive
And we all know that caps take time to charge,
and draw decreasing currents as they do charge.
So initially they look like short circuits. In all other ways the PD
works very well.
Unspoken here is the reaction of the
This puts me firmly on the side of specifying the
behavior of both the PSE and the PD during the start up mode. In addition,
(now that I am thinking about this, I was not in St. Louis), should there be
some specification for startup during the classification process? (Now
I am getting away from the issue.) The point being that System Engineering
of the whole Ethernet link could possibly create a system which would run
perfectly once it is up. But because of the lack of power up specification
would not start. Modeling both the PSE and PD during start up mode would
prevent this from occurring.
Another point. I fully
understand the engineering reasons for increasing the cap at the PD. But in
the above example this clearly did not help during the start up
So I have a couple of questions.
1) Do we need perfect stability? Or is it possible that
some instability can be acceptable? ( I am defining stability as the change
in voltage or current over time.) I would guess that getting perfect
stability is not possible. But some low bandwidth instability would be
possible without impacting system performance. But where would this
instability begin to impact the signaling?
2) Is there a trade off between
instability and cap size, which will allow a minimum size cap to be
Thank you for your input.
----- Original Message -----
From: Rick Brooks <mailto:ribrooks@xxxxxxxxxxxxxxxxxx>
To: stds-802-3-pwrviamdi@xxxxxxxx <mailto:stds-802-3-pwrviamdi@xxxxxxxx>
Sent: Wednesday, May 30, 2001 7:01 PM
Subject: insuring the stability of
I just wanted to voice one concern that I have regarding
power ramp up, and continuous power modes.
I was reminded of this issue
when I was simulating the current limits in the PSE and PD and
oscillations on the cable during startup. Yair's Pspice circuit
does not have these problems
due to the fact that there are Op-amps in the current
limit feedback loops (i.e. band limited).
It seems to me that we do not yet have a
defined and specified behavior that will insure that the DTE power will
a stable way.
How do we guarantee that a PD from vendor "A" will not oscillate
when connected to a PSE from vendor "B"?
The PD as an electrical load
needs to be dominated by a capacitive reactance.
I think that we all agree,
but this has not yet been specified.
During power ramp up, either the PSE or PD
current limit will be in effect, so we need to specify the
power ramp up.
At the present time, what behavior is specified
to insure that the PSE feedback loops,
either to regulate the
output voltage, or to limit the current (protection circuits),
will not oscillate with the
longest UTP cable or the PD?
It seems that we need to address these issues
or we do not have a complete standard.
1) specify the maximum loop
bandwidths of the PSE and PD loops so that any such system will
a lumped circuit. In other words, spec the loop bandwidth so that it is
about 6 to 10
times smaller than 1/lambda of the maximum length UTP
We do not
want sudden load changes to cause oscillation or ringing, for
rate helps, but it is a large signal behavior only.
2) specify a minimum phase margin into a
"standard" PD load (whatever that is)
3) specify a maximum gain at the UTP bandwidth
at the longest cable.
4) both the PSE and PD need to have a specified
Any other ideas or discussion on this
you power guys???